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Add a Thumb2 t2RSBrr instruction for disassembly only.

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This fixes another part of PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111057 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-08-13 23:24:25 +00:00
parent 0a2b2a1497
commit 20d8e4e7aa
2 changed files with 22 additions and 5 deletions
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23
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -259,9 +259,9 @@ multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
/// reversed. It doesn't define the 'rr' form since it's handled by its
/// T2I_bin_irs counterpart.
multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
/// reversed. The 'rr' form is only defined for the disassembler; for codegen
/// it is equivalent to the T2I_bin_irs counterpart.
multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
// shifted imm
def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
opc, ".w\t$dst, $rhs, $lhs",
@ -272,6 +272,18 @@ multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
let Inst{20} = ?; // The S bit.
let Inst{15} = 0;
}
// register
def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr,
opc, "\t$dst, $rhs, $lhs",
[(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
let Inst{20} = ?; // The S bit.
let Inst{14-12} = 0b000; // imm3
let Inst{7-6} = 0b00; // imm2
let Inst{5-4} = 0b00; // type
}
// shifted register
def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
opc, "\t$dst, $rhs, $lhs",
@ -461,7 +473,8 @@ multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
}
}
/// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
/// version is not needed since this is only for codegen.
let Defs = [CPSR] in {
multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
// shifted imm
@ -1387,7 +1400,7 @@ defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
// RSB
defm t2RSB : T2I_rbin_is <0b1110, "rsb",
defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
BinOpFrag<(sub node:$LHS, node:$RHS)>>;
defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
BinOpFrag<(subc node:$LHS, node:$RHS)>>;

4
test/MC/Disassembler/thumb-tests.txt
View File

@ -51,6 +51,10 @@
# CHECK: rsbs r0, r0, #0
0x40 0x42
# CHECK-NOT: rsb r0, r2, r0, lsl #0
# CHECK: rsb r0, r2, r0
0xc2 0xeb 0x00 0x00
# CHECK-NOT: ssat r0, #17, r12, lsl #0
# CHECK: ssat r0, #17, r12
0x0c 0xf3 0x10 0x00