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[Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers.

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Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182219 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju 2013-05-19 20:07:20 +00:00
parent 233a4d7124
commit 21886a495a
3 changed files with 24 additions and 11 deletions
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14
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -20,6 +20,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetInstrInfo.h"
@ -28,6 +29,10 @@
using namespace llvm;
static cl::opt<bool>
ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
cl::desc("Reserve application registers (%g2-%g4)"));
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
const TargetInstrInfo &tii)
: SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
@ -43,14 +48,21 @@ BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
// FIXME: G1 reserved for now for large imm generation by frame code.
Reserved.set(SP::G1);
//G1-G4 can be used in applications.
if (ReserveAppRegisters) {
Reserved.set(SP::G2);
Reserved.set(SP::G3);
Reserved.set(SP::G4);
}
//G5 is not reserved in 64 bit mode.
if (!Subtarget.is64Bit())
Reserved.set(SP::G5);
Reserved.set(SP::O6);
Reserved.set(SP::I6);
Reserved.set(SP::I7);
Reserved.set(SP::G0);
Reserved.set(SP::G5);
Reserved.set(SP::G6);
Reserved.set(SP::G7);
return Reserved;

13
lib/Target/Sparc/SparcRegisterInfo.td
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@ -144,18 +144,19 @@ def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>;
// register class for that. The i64 type is included here to allow i64 patterns
// using the integer instructions.
def IntRegs : RegisterClass<"SP", [i32, i64], 32,
(add L0, L1, L2, L3, L4, L5, L6,
L7, I0, I1, I2, I3, I4, I5,
O0, O1, O2, O3, O4, O5, O7,
(add I0, I1, I2, I3, I4, I5,
G1,
// Non-allocatable regs:
G2, G3, G4, // FIXME: OK for use only in
G2, G3, G4, // OK for use only in
// applications, not libraries.
G5, // OK for use in 64 bit mode.
L0, L1, L2, L3, L4, L5, L6, L7,
O0, O1, O2, O3, O4, O5, O7,
// Non-allocatable regs:
O6, // stack ptr
I6, // frame ptr
I7, // return address
G0, // constant zero
G5, G6, G7 // reserved for kernel
G6, G7 // reserved for kernel
)>;
// Register class for 64-bit mode, with a 64-bit spill slot size.

2
test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
View File

@ -97,7 +97,7 @@ entry:
;CHECK-NEXT: nop
%0 = add nsw i32 %i0, 2
%1 = add nsw i32 %i0, 3
tail call void asm sideeffect "", "r,r,~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{o0},~{o1},~{o2},~{o3},~{o4}"(i32 %0, i32 %1)
tail call void asm sideeffect "", "r,r,~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o6},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7}"(i32 %0, i32 %1)
%2 = add nsw i32 %0, %1
%3 = tail call i32 @bar(i32 %2)
ret i32 %3