6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-07 14:33:15 +00:00
Code Issues Projects Releases Wiki Activity

More PPC32 -> PPC changes, as well as merging some classes that were

Browse Source 
redundant after the change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-10-16 05:39:50 +00:00
parent 5024d93c8b
commit 21e463b2bf
20 changed files with 152 additions and 170 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -1,4 +1,4 @@
//===-- PPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --===//
//===-- PPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --------=//
//
// The LLVM Compiler Infrastructure
//
@ -57,8 +57,8 @@ namespace {
return "PowerPC Assembly Printer";
}
PowerPCTargetMachine &getTM() {
return static_cast<PowerPCTargetMachine&>(TM);
PPCTargetMachine &getTM() {
return static_cast<PPCTargetMachine&>(TM);
}
unsigned enumRegToMachineReg(unsigned enumReg) {

4
lib/Target/PowerPC/PPCBranchSelector.cpp
View File

@ -1,4 +1,4 @@
//===-- PowerPCBranchSelector.cpp - Emit long conditional branches-*- C++ -*-=//
//===-- PPCBranchSelector.cpp - Emit long conditional branches-----*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
@ -107,7 +107,7 @@ namespace {
int Displacement = OffsetMap[trueMBB] - ByteCount;
unsigned Opcode = MBBI->getOperand(1).getImmedValue();
unsigned CRReg = MBBI->getOperand(0).getReg();
unsigned Inverted = PPC32InstrInfo::invertPPCBranchOpcode(Opcode);
unsigned Inverted = PPCInstrInfo::invertPPCBranchOpcode(Opcode);
if (Displacement >= -32768 && Displacement <= 32767) {
BuildMI(*MBB, MBBJ, Opcode, 2).addReg(CRReg).addMBB(trueMBB);

6
lib/Target/PowerPC/PPCCodeEmitter.cpp
View File

@ -1,4 +1,4 @@
//===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC32 -----*- C++ -*-=//
//===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC32 -------*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
@ -74,8 +74,8 @@ namespace {
/// of functions. This method should returns true if machine code emission is
/// not supported.
///
bool PPC32TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE) {
bool PPCTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE) {
// Machine code emitter pass for PowerPC
PM.add(new PPCCodeEmitter(*this, MCE));
// Delete machine code for this function after emitting it

8
lib/Target/PowerPC/PPCFrameInfo.h
View File

@ -1,4 +1,4 @@
//===-- PowerPCFrameInfo.h - Define TargetFrameInfo for PowerPC -*- C++ -*-===//
//===-- PPCFrameInfo.h - Define TargetFrameInfo for PowerPC -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -8,7 +8,7 @@
//===----------------------------------------------------------------------===//
//
//
//----------------------------------------------------------------------------
//===----------------------------------------------------------------------===//
#ifndef POWERPC_FRAMEINFO_H
#define POWERPC_FRAMEINFO_H
@ -19,12 +19,12 @@
namespace llvm {
class PowerPCFrameInfo: public TargetFrameInfo {
class PPCFrameInfo: public TargetFrameInfo {
const TargetMachine &TM;
std::pair<unsigned, int> LR[1];
public:
PowerPCFrameInfo(const TargetMachine &tm, bool LP64)
PPCFrameInfo(const TargetMachine &tm, bool LP64)
: TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), TM(tm) {
LR[0].first = PPC::LR;
LR[0].second = LP64 ? 16 : 8;

8
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -1,4 +1,4 @@
//===-- PPC32ISelDAGToDAG.cpp - PPC32 pattern matching inst selector ------===//
//===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// This file defines a pattern matching instruction selector for 32 bit PowerPC,
// This file defines a pattern matching instruction selector for PowerPC,
// converting from a legalized dag to a PPC dag.
//
//===----------------------------------------------------------------------===//
@ -37,11 +37,11 @@ namespace {
/// instructions for SelectionDAG operations.
///
class PPC32DAGToDAGISel : public SelectionDAGISel {
PPC32TargetLowering PPC32Lowering;
PPCTargetLowering PPCLowering;
unsigned GlobalBaseReg;
public:
PPC32DAGToDAGISel(TargetMachine &TM)
: SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
: SelectionDAGISel(PPCLowering), PPCLowering(TM) {}
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary

36
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1,4 +1,4 @@
//===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Implementation ---------===//
//===-- PPCISelLowering.cpp - PPC32 DAG Lowering Implementation -----------===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// This file implements the PPC32ISelLowering class.
// This file implements the PPCISelLowering class.
//
//===----------------------------------------------------------------------===//
@ -22,7 +22,7 @@
#include "llvm/Function.h"
using namespace llvm;
PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
: TargetLowering(TM) {
// Fold away setcc operations if possible.
@ -125,7 +125,7 @@ static bool isFloatingPointZero(SDOperand Op) {
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Wasn't expecting to be able to lower this!");
case ISD::FP_TO_SINT: {
@ -311,7 +311,7 @@ SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
}
std::vector<SDOperand>
PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
//
// add beautiful description of PPC stack frame format, or at least some docs
//
@ -490,11 +490,11 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
}
std::pair<SDOperand, SDOperand>
PPC32TargetLowering::LowerCallTo(SDOperand Chain,
const Type *RetTy, bool isVarArg,
unsigned CallingConv, bool isTailCall,
SDOperand Callee, ArgListTy &Args,
SelectionDAG &DAG) {
PPCTargetLowering::LowerCallTo(SDOperand Chain,
const Type *RetTy, bool isVarArg,
unsigned CallingConv, bool isTailCall,
SDOperand Callee, ArgListTy &Args,
SelectionDAG &DAG) {
// args_to_use will accumulate outgoing args for the ISD::CALL case in
// SelectExpr to use to put the arguments in the appropriate registers.
std::vector<SDOperand> args_to_use;
@ -687,8 +687,8 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
return std::make_pair(RetVal, Chain);
}
SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
Value *VAListV, SelectionDAG &DAG) {
SDOperand PPCTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
Value *VAListV, SelectionDAG &DAG) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
@ -697,9 +697,9 @@ SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
}
std::pair<SDOperand,SDOperand>
PPC32TargetLowering::LowerVAArg(SDOperand Chain,
SDOperand VAListP, Value *VAListV,
const Type *ArgTy, SelectionDAG &DAG) {
PPCTargetLowering::LowerVAArg(SDOperand Chain,
SDOperand VAListP, Value *VAListV,
const Type *ArgTy, SelectionDAG &DAG) {
MVT::ValueType ArgVT = getValueType(ArgTy);
SDOperand VAList =
@ -721,7 +721,7 @@ PPC32TargetLowering::LowerVAArg(SDOperand Chain,
}
std::pair<SDOperand, SDOperand> PPC32TargetLowering::
std::pair<SDOperand, SDOperand> PPCTargetLowering::
LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
SelectionDAG &DAG) {
assert(0 && "LowerFrameReturnAddress unimplemented");
@ -729,8 +729,8 @@ LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
}
MachineBasicBlock *
PPC32TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
MI->getOpcode() == PPC::SELECT_CC_F4 ||
MI->getOpcode() == PPC::SELECT_CC_F8) &&

6
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -1,4 +1,4 @@
//===-- PPC32ISelLowering.h - PPC32 DAG Lowering Interface ------*- C++ -*-===//
//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -41,11 +41,11 @@ namespace llvm {
};
}
class PPC32TargetLowering : public TargetLowering {
class PPCTargetLowering : public TargetLowering {
int VarArgsFrameIndex; // FrameIndex for start of varargs area.
int ReturnAddrIndex; // FrameIndex for return slot.
public:
PPC32TargetLowering(TargetMachine &TM);
PPCTargetLowering(TargetMachine &TM);
/// LowerOperation - Provide custom lowering hooks for some operations.
///

4
lib/Target/PowerPC/PPCISelPattern.cpp
View File

@ -44,7 +44,7 @@ Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
//===--------------------------------------------------------------------===//
class ISel : public SelectionDAGISel {
PPC32TargetLowering PPC32Lowering;
PPCTargetLowering PPCLowering;
SelectionDAG *ISelDAG; // Hack to support us having a dag->dag transform
// for sdiv and udiv until it is put into the future
// dag combiner.
@ -58,7 +58,7 @@ class ISel : public SelectionDAGISel {
bool GlobalBaseInitialized;
bool RecordSuccess;
public:
ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM),
ISel(TargetMachine &TM) : SelectionDAGISel(PPCLowering), PPCLowering(TM),
ISelDAG(0) {}
/// runOnFunction - Override this function in order to reset our per-function

2
lib/Target/PowerPC/PPCInstrBuilder.h
View File

@ -1,4 +1,4 @@
//===-- PowerPCInstrBuilder.h - Aides for building PPC insts ----*- C++ -*-===//
//===-- PPCInstrBuilder.h - Aides for building PPC insts --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

12
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -1,4 +1,4 @@
//===- PPC32InstrInfo.cpp - PowerPC32 Instruction Information ---*- C++ -*-===//
//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -18,12 +18,12 @@
#include <iostream>
using namespace llvm;
PPC32InstrInfo::PPC32InstrInfo()
PPCInstrInfo::PPCInstrInfo()
: TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])) {}
bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
if (oc == PPC::OR) { // or r1, r2, r2
assert(MI.getNumOperands() == 3 &&
@ -80,7 +80,7 @@ bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
// commuteInstruction - We can commute rlwimi instructions, but only if the
// rotate amt is zero. We also have to munge the immediates a bit.
MachineInstr *PPC32InstrInfo::commuteInstruction(MachineInstr *MI) const {
MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
// Normal instructions can be commuted the obvious way.
if (MI->getOpcode() != PPC::RLWIMI)
return TargetInstrInfo::commuteInstruction(MI);

8
lib/Target/PowerPC/PPCInstrInfo.h
View File

@ -1,4 +1,4 @@
//===- PPC32InstrInfo.h - PowerPC32 Instruction Information -----*- C++ -*-===//
//===- PPCInstrInfo.h - PowerPC32 Instruction Information -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -20,10 +20,10 @@
namespace llvm {
class PPC32InstrInfo : public TargetInstrInfo {
const PPC32RegisterInfo RI;
class PPCInstrInfo : public TargetInstrInfo {
const PPCRegisterInfo RI;
public:
PPC32InstrInfo();
PPCInstrInfo();
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should

12
lib/Target/PowerPC/PPCJITInfo.cpp
View File

@ -1,4 +1,4 @@
//===-- PPC32JITInfo.cpp - Implement the JIT interfaces for the PowerPC ---===//
//===-- PPCJITInfo.cpp - Implement the JIT interfaces for the PowerPC -----===//
//
// The LLVM Compiler Infrastructure
//
@ -154,12 +154,12 @@ extern "C" void PPC32CompilationCallbackC(unsigned *IntRegs, double *FPRegs) {
TargetJITInfo::LazyResolverFn
PPC32JITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
JITCompilerFunction = Fn;
return PPC32CompilationCallback;
}
void *PPC32JITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
void *PPCJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
// If this is just a call to an external function, emit a branch instead of a
// call. The code is the same except for one bit of the last instruction.
if (Fn != PPC32CompilationCallback) {
@ -187,8 +187,8 @@ void *PPC32JITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
}
void PPC32JITInfo::relocate(void *Function, MachineRelocation *MR,
unsigned NumRelocs, unsigned char* GOTBase) {
void PPCJITInfo::relocate(void *Function, MachineRelocation *MR,
unsigned NumRelocs, unsigned char* GOTBase) {
for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
intptr_t ResultPtr = (intptr_t)MR->getResultPointer();
@ -238,6 +238,6 @@ void PPC32JITInfo::relocate(void *Function, MachineRelocation *MR,
}
}
void PPC32JITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
void PPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
EmitBranchToAt(Old, New, false);
}

12
lib/Target/PowerPC/PPCJITInfo.h
View File

@ -19,24 +19,18 @@
namespace llvm {
class TargetMachine;
// FIXME: Merge into one PPCJITInfo class.
class PowerPCJITInfo : public TargetJITInfo {
class PPCJITInfo : public TargetJITInfo {
protected:
TargetMachine &TM;
public:
PowerPCJITInfo(TargetMachine &tm) : TM(tm) {useGOT = 0;}
PPCJITInfo(TargetMachine &tm) : TM(tm) {useGOT = 0;}
/// addPassesToJITCompile - Add passes to the specified pass manager to
/// implement a fast dynamic compiler for this target. Return true if this
/// is not supported for this target.
///
virtual void addPassesToJITCompile(FunctionPassManager &PM);
};
class PPC32JITInfo : public PowerPCJITInfo {
public:
PPC32JITInfo(TargetMachine &tm) : PowerPCJITInfo(tm) {}
virtual void *emitFunctionStub(void *Fn, MachineCodeEmitter &MCE);
virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
virtual void relocate(void *Function, MachineRelocation *MR,

44
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -1,4 +1,4 @@
//===- PPC32RegisterInfo.cpp - PowerPC32 Register Information ---*- C++ -*-===//
//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC32 implementation of the MRegisterInfo class.
// This file contains the PowerPC implementation of the MRegisterInfo class.
//
//===----------------------------------------------------------------------===//
@ -31,7 +31,7 @@
#include <iostream>
using namespace llvm;
PPC32RegisterInfo::PPC32RegisterInfo()
PPCRegisterInfo::PPCRegisterInfo()
: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
@ -44,10 +44,10 @@ PPC32RegisterInfo::PPC32RegisterInfo()
}
void
PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
if (SrcReg == PPC::LR) {
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
@ -67,7 +67,7 @@ PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
}
void
PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const {
@ -89,10 +89,10 @@ PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
}
}
void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
MachineInstr *I;
if (RC == PPC32::GPRCRegisterClass) {
@ -109,8 +109,8 @@ void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
}
}
unsigned PPC32RegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
int &FrameIndex) const {
unsigned PPCRegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
int &FrameIndex) const {
switch (MI->getOpcode()) {
default: break;
case PPC::LWZ:
@ -128,9 +128,9 @@ unsigned PPC32RegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
/// copy instructions, turning them into load/store instructions.
MachineInstr *PPC32RegisterInfo::foldMemoryOperand(MachineInstr *MI,
unsigned OpNum,
int FrameIndex) const {
MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
unsigned OpNum,
int FrameIndex) const {
// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
// it takes more than one instruction to store it.
unsigned Opc = MI->getOpcode();
@ -180,7 +180,7 @@ static bool hasFP(MachineFunction &MF) {
return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
}
void PPC32RegisterInfo::
void PPCRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
if (hasFP(MF)) {
@ -211,7 +211,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
}
void
PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
unsigned i = 0;
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
@ -261,7 +261,7 @@ PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
}
void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const {
void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -320,8 +320,8 @@ void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const {
}
}
void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
MachineInstr *MI;

6
lib/Target/PowerPC/PPCRegisterInfo.h
View File

@ -1,4 +1,4 @@
//===- PPC32RegisterInfo.h - PowerPC32 Register Information Impl -*- C++ -*-==//
//===- PPCRegisterInfo.h - PowerPC Register Information Impl -----*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
@ -22,10 +22,10 @@ namespace llvm {
class Type;
class PPC32RegisterInfo : public PPCGenRegisterInfo {
class PPCRegisterInfo : public PPCGenRegisterInfo {
std::map<unsigned, unsigned> ImmToIdxMap;
public:
PPC32RegisterInfo();
PPCRegisterInfo();
/// Code Generation virtual methods...
void storeRegToStackSlot(MachineBasicBlock &MBB,

2
lib/Target/PowerPC/PPCRelocations.h
View File

@ -1,4 +1,4 @@
//===- PPC32Relocations.h - PPC32 Code Relocations --------------*- C++ -*-===//
//===- PPCRelocations.h - PPC32 Code Relocations ----------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/PowerPC/PPCSubtarget.h
View File

@ -1,4 +1,4 @@
//=====-- PowerPCSubtarget.h - Define Subtarget for the PPC ---*- C++ -*--====//
//=====-- PPCSubtarget.h - Define Subtarget for the PPC -------*- C++ -*--====//
//
// The LLVM Compiler Infrastructure
//

80
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -1,4 +1,4 @@
//===-- PowerPCTargetMachine.cpp - Define TargetMachine for PowerPC -------===//
//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
//
// The LLVM Compiler Infrastructure
//
@ -29,30 +29,15 @@
using namespace llvm;
namespace {
const char *PPC32ID = "PowerPC/32bit";
static cl::opt<bool> DisablePPCDAGDAG("disable-ppc-dag-isel", cl::Hidden,
cl::desc("Disable DAG-to-DAG isel for PPC"));
// Register the targets
RegisterTarget<PPC32TargetMachine>
X("ppc32", " PowerPC 32-bit");
RegisterTarget<PPCTargetMachine>
X("ppc32", " PowerPC");
}
PowerPCTargetMachine::PowerPCTargetMachine(const std::string &name,
IntrinsicLowering *IL,
const Module &M,
const std::string &FS,
const TargetData &TD,
const PowerPCFrameInfo &TFI)
: TargetMachine(name, IL, TD), FrameInfo(TFI), Subtarget(M, FS) {
if (TargetDefault == PPCTarget) {
if (Subtarget.isAIX()) PPCTarget = TargetAIX;
if (Subtarget.isDarwin()) PPCTarget = TargetDarwin;
}
}
unsigned PPC32TargetMachine::getJITMatchQuality() {
unsigned PPCTargetMachine::getJITMatchQuality() {
#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)
return 10;
#else
@ -60,12 +45,38 @@ unsigned PPC32TargetMachine::getJITMatchQuality() {
#endif
}
unsigned PPCTargetMachine::getModuleMatchQuality(const Module &M) {
// We strongly match "powerpc-*".
std::string TT = M.getTargetTriple();
if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-")
return 20;
if (M.getEndianness() == Module::BigEndian &&
M.getPointerSize() == Module::Pointer32)
return 10; // Weak match
else if (M.getEndianness() != Module::AnyEndianness ||
M.getPointerSize() != Module::AnyPointerSize)
return 0; // Match for some other target
return getJITMatchQuality()/2;
}
PPCTargetMachine::PPCTargetMachine(const Module &M, IntrinsicLowering *IL,
const std::string &FS)
: TargetMachine("PowerPC", IL, false, 4, 4, 4, 4, 4, 4, 2, 1, 1),
Subtarget(M, FS), FrameInfo(*this, false), JITInfo(*this) {
if (TargetDefault == PPCTarget) {
if (Subtarget.isAIX()) PPCTarget = TargetAIX;
if (Subtarget.isDarwin()) PPCTarget = TargetDarwin;
}
}
/// addPassesToEmitFile - Add passes to the specified pass manager to implement
/// a static compiler for this target.
///
bool PowerPCTargetMachine::addPassesToEmitFile(PassManager &PM,
std::ostream &Out,
CodeGenFileType FileType) {
bool PPCTargetMachine::addPassesToEmitFile(PassManager &PM,
std::ostream &Out,
CodeGenFileType FileType) {
if (FileType != TargetMachine::AssemblyFile) return true;
// Run loop strength reduction before anything else.
@ -121,7 +132,7 @@ bool PowerPCTargetMachine::addPassesToEmitFile(PassManager &PM,
return false;
}
void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
void PPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
// The JIT does not support or need PIC.
PICEnabled = false;
@ -159,26 +170,3 @@ void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
PM.add(createMachineFunctionPrinterPass(&std::cerr));
}
/// PowerPCTargetMachine ctor - Create an ILP32 architecture model
///
PPC32TargetMachine::PPC32TargetMachine(const Module &M, IntrinsicLowering *IL,
const std::string &FS)
: PowerPCTargetMachine(PPC32ID, IL, M, FS,
TargetData(PPC32ID,false,4,4,4,4,4,4,2,1,1),
PowerPCFrameInfo(*this, false)), JITInfo(*this) {}
unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {
// We strongly match "powerpc-*".
std::string TT = M.getTargetTriple();
if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-")
return 20;
if (M.getEndianness() == Module::BigEndian &&
M.getPointerSize() == Module::Pointer32)
return 10; // Weak match
else if (M.getEndianness() != Module::AnyEndianness ||
M.getPointerSize() != Module::AnyPointerSize)
return 0; // Match for some other target
return getJITMatchQuality()/2;
}

51
lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -1,4 +1,4 @@
//===-- PPC32TargetMachine.h - Define TargetMachine for PowerPC -*- C++ -*-=//
//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC -----*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
#ifndef POWERPC32_TARGETMACHINE_H
#define POWERPC32_TARGETMACHINE_H
#ifndef PPC_TARGETMACHINE_H
#define PPC_TARGETMACHINE_H
#include "PPCFrameInfo.h"
#include "PPCSubtarget.h"
@ -26,47 +26,34 @@ class IntrinsicLowering;
class GlobalValue;
class IntrinsicLowering;
// FIXME: Merge into only subclass.
class PowerPCTargetMachine : public TargetMachine {
PowerPCFrameInfo FrameInfo;
PPCSubtarget Subtarget;
protected:
PowerPCTargetMachine(const std::string &name, IntrinsicLowering *IL,
const Module &M, const std::string &FS,
const TargetData &TD,
const PowerPCFrameInfo &TFI);
class PPCTargetMachine : public TargetMachine {
PPCInstrInfo InstrInfo;
PPCSubtarget Subtarget;
PPCFrameInfo FrameInfo;
PPCJITInfo JITInfo;
public:
PPCTargetMachine(const Module &M, IntrinsicLowering *IL,
const std::string &FS);
virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual TargetJITInfo *getJITInfo() { return &JITInfo; }
virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; }
virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out,
CodeGenFileType FileType);
};
class PPC32TargetMachine : public PowerPCTargetMachine {
PPC32InstrInfo InstrInfo;
PPC32JITInfo JITInfo;
public:
PPC32TargetMachine(const Module &M, IntrinsicLowering *IL,
const std::string &FS);
virtual const PPC32InstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const MRegisterInfo *getRegisterInfo() const {
virtual const MRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
virtual TargetJITInfo *getJITInfo() {
return &JITInfo;
}
static unsigned getJITMatchQuality();
static unsigned getModuleMatchQuality(const Module &M);
virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out,
CodeGenFileType FileType);
bool addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE);
};
} // end namespace llvm
#endif

13
lib/Target/PowerPC/README.txt
View File

@ -105,3 +105,16 @@ mode.
Implement Newton-Rhapson method for improving estimate instructions to the
correct accuracy, and implementing divide as multiply by reciprocal when it has
more than one use. Itanium will want this too.
===-------------------------------------------------------------------------===
int foo(int a, int b) { return a == b ? 16 : 0; }
_foo:
cmpw cr7, r3, r4
mfcr r2
rlwinm r2, r2, 31, 31, 31
slwi r3, r2, 4
blr
If we exposed the srl & mask ops after the MFCR that we are doing to select
the correct CR bit, then we could fold the slwi into the rlwinm before it.