6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-08 21:32:39 +00:00
Code Issues Projects Releases Wiki Activity

ARM prefix asmparser operand kind enums for readability.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141438 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-10-07 23:24:09 +00:00
parent 2acf638216
commit 21ff17ce1b
1 changed files with 172 additions and 172 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

344
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -242,28 +242,28 @@ namespace {
/// instruction. /// instruction.
class ARMOperand : public MCParsedAsmOperand { class ARMOperand : public MCParsedAsmOperand {
enum KindTy { enum KindTy {
CondCode, k_CondCode,
CCOut, k_CCOut,
ITCondMask, k_ITCondMask,
CoprocNum, k_CoprocNum,
CoprocReg, k_CoprocReg,
Immediate, k_Immediate,
FPImmediate, k_FPImmediate,
MemBarrierOpt, k_MemBarrierOpt,
Memory, k_Memory,
PostIndexRegister, k_PostIndexRegister,
MSRMask, k_MSRMask,
ProcIFlags, k_ProcIFlags,
Register, k_Register,
RegisterList, k_RegisterList,
DPRRegisterList, k_DPRRegisterList,
SPRRegisterList, k_SPRRegisterList,
ShiftedRegister, k_ShiftedRegister,
ShiftedImmediate, k_ShiftedImmediate,
ShifterImmediate, k_ShifterImmediate,
RotateImmediate, k_RotateImmediate,
BitfieldDescriptor, k_BitfieldDescriptor,
Token k_Token
} Kind; } Kind;
SMLoc StartLoc, EndLoc; SMLoc StartLoc, EndLoc;
@ -361,62 +361,62 @@ public:
StartLoc = o.StartLoc; StartLoc = o.StartLoc;
EndLoc = o.EndLoc; EndLoc = o.EndLoc;
switch (Kind) { switch (Kind) {
case CondCode: case k_CondCode:
CC = o.CC; CC = o.CC;
break; break;
case ITCondMask: case k_ITCondMask:
ITMask = o.ITMask; ITMask = o.ITMask;
break; break;
case Token: case k_Token:
Tok = o.Tok; Tok = o.Tok;
break; break;
case CCOut: case k_CCOut:
case Register: case k_Register:
Reg = o.Reg; Reg = o.Reg;
break; break;
case RegisterList: case k_RegisterList:
case DPRRegisterList: case k_DPRRegisterList:
case SPRRegisterList: case k_SPRRegisterList:
Registers = o.Registers; Registers = o.Registers;
break; break;
case CoprocNum: case k_CoprocNum:
case CoprocReg: case k_CoprocReg:
Cop = o.Cop; Cop = o.Cop;
break; break;
case Immediate: case k_Immediate:
Imm = o.Imm; Imm = o.Imm;
break; break;
case FPImmediate: case k_FPImmediate:
FPImm = o.FPImm; FPImm = o.FPImm;
break; break;
case MemBarrierOpt: case k_MemBarrierOpt:
MBOpt = o.MBOpt; MBOpt = o.MBOpt;
break; break;
case Memory: case k_Memory:
Mem = o.Mem; Mem = o.Mem;
break; break;
case PostIndexRegister: case k_PostIndexRegister:
PostIdxReg = o.PostIdxReg; PostIdxReg = o.PostIdxReg;
break; break;
case MSRMask: case k_MSRMask:
MMask = o.MMask; MMask = o.MMask;
break; break;
case ProcIFlags: case k_ProcIFlags:
IFlags = o.IFlags; IFlags = o.IFlags;
break; break;
case ShifterImmediate: case k_ShifterImmediate:
ShifterImm = o.ShifterImm; ShifterImm = o.ShifterImm;
break; break;
case ShiftedRegister: case k_ShiftedRegister:
RegShiftedReg = o.RegShiftedReg; RegShiftedReg = o.RegShiftedReg;
break; break;
case ShiftedImmediate: case k_ShiftedImmediate:
RegShiftedImm = o.RegShiftedImm; RegShiftedImm = o.RegShiftedImm;
break; break;
case RotateImmediate: case k_RotateImmediate:
RotImm = o.RotImm; RotImm = o.RotImm;
break; break;
case BitfieldDescriptor: case k_BitfieldDescriptor:
Bitfield = o.Bitfield; Bitfield = o.Bitfield;
break; break;
} }
@ -428,66 +428,66 @@ public:
SMLoc getEndLoc() const { return EndLoc; } SMLoc getEndLoc() const { return EndLoc; }
ARMCC::CondCodes getCondCode() const { ARMCC::CondCodes getCondCode() const {
assert(Kind == CondCode && "Invalid access!"); assert(Kind == k_CondCode && "Invalid access!");
return CC.Val; return CC.Val;
} }
unsigned getCoproc() const { unsigned getCoproc() const {
assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!"); assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
return Cop.Val; return Cop.Val;
} }
StringRef getToken() const { StringRef getToken() const {
assert(Kind == Token && "Invalid access!"); assert(Kind == k_Token && "Invalid access!");
return StringRef(Tok.Data, Tok.Length); return StringRef(Tok.Data, Tok.Length);
} }
unsigned getReg() const { unsigned getReg() const {
assert((Kind == Register || Kind == CCOut) && "Invalid access!"); assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
return Reg.RegNum; return Reg.RegNum;
} }
const SmallVectorImpl<unsigned> &getRegList() const { const SmallVectorImpl<unsigned> &getRegList() const {
assert((Kind == RegisterList || Kind == DPRRegisterList || assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
Kind == SPRRegisterList) && "Invalid access!"); Kind == k_SPRRegisterList) && "Invalid access!");
return Registers; return Registers;
} }
const MCExpr *getImm() const { const MCExpr *getImm() const {
assert(Kind == Immediate && "Invalid access!"); assert(Kind == k_Immediate && "Invalid access!");
return Imm.Val; return Imm.Val;
} }
unsigned getFPImm() const { unsigned getFPImm() const {
assert(Kind == FPImmediate && "Invalid access!"); assert(Kind == k_FPImmediate && "Invalid access!");
return FPImm.Val; return FPImm.Val;
} }
ARM_MB::MemBOpt getMemBarrierOpt() const { ARM_MB::MemBOpt getMemBarrierOpt() const {
assert(Kind == MemBarrierOpt && "Invalid access!"); assert(Kind == k_MemBarrierOpt && "Invalid access!");
return MBOpt.Val; return MBOpt.Val;
} }
ARM_PROC::IFlags getProcIFlags() const { ARM_PROC::IFlags getProcIFlags() const {
assert(Kind == ProcIFlags && "Invalid access!"); assert(Kind == k_ProcIFlags && "Invalid access!");
return IFlags.Val; return IFlags.Val;
} }
unsigned getMSRMask() const { unsigned getMSRMask() const {
assert(Kind == MSRMask && "Invalid access!"); assert(Kind == k_MSRMask && "Invalid access!");
return MMask.Val; return MMask.Val;
} }
bool isCoprocNum() const { return Kind == CoprocNum; } bool isCoprocNum() const { return Kind == k_CoprocNum; }
bool isCoprocReg() const { return Kind == CoprocReg; } bool isCoprocReg() const { return Kind == k_CoprocReg; }
bool isCondCode() const { return Kind == CondCode; } bool isCondCode() const { return Kind == k_CondCode; }
bool isCCOut() const { return Kind == CCOut; } bool isCCOut() const { return Kind == k_CCOut; }
bool isITMask() const { return Kind == ITCondMask; } bool isITMask() const { return Kind == k_ITCondMask; }
bool isITCondCode() const { return Kind == CondCode; } bool isITCondCode() const { return Kind == k_CondCode; }
bool isImm() const { return Kind == Immediate; } bool isImm() const { return Kind == k_Immediate; }
bool isFPImm() const { return Kind == FPImmediate; } bool isFPImm() const { return Kind == k_FPImmediate; }
bool isImm8s4() const { bool isImm8s4() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -495,7 +495,7 @@ public:
return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
} }
bool isImm0_1020s4() const { bool isImm0_1020s4() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -503,7 +503,7 @@ public:
return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
} }
bool isImm0_508s4() const { bool isImm0_508s4() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -511,7 +511,7 @@ public:
return ((Value & 3) == 0) && Value >= 0 && Value <= 508; return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
} }
bool isImm0_255() const { bool isImm0_255() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -519,7 +519,7 @@ public:
return Value >= 0 && Value < 256; return Value >= 0 && Value < 256;
} }
bool isImm0_7() const { bool isImm0_7() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -527,7 +527,7 @@ public:
return Value >= 0 && Value < 8; return Value >= 0 && Value < 8;
} }
bool isImm0_15() const { bool isImm0_15() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -535,7 +535,7 @@ public:
return Value >= 0 && Value < 16; return Value >= 0 && Value < 16;
} }
bool isImm0_31() const { bool isImm0_31() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -543,7 +543,7 @@ public:
return Value >= 0 && Value < 32; return Value >= 0 && Value < 32;
} }
bool isImm1_16() const { bool isImm1_16() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -551,7 +551,7 @@ public:
return Value > 0 && Value < 17; return Value > 0 && Value < 17;
} }
bool isImm1_32() const { bool isImm1_32() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -559,7 +559,7 @@ public:
return Value > 0 && Value < 33; return Value > 0 && Value < 33;
} }
bool isImm0_65535() const { bool isImm0_65535() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -567,7 +567,7 @@ public:
return Value >= 0 && Value < 65536; return Value >= 0 && Value < 65536;
} }
bool isImm0_65535Expr() const { bool isImm0_65535Expr() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
// If it's not a constant expression, it'll generate a fixup and be // If it's not a constant expression, it'll generate a fixup and be
@ -577,7 +577,7 @@ public:
return Value >= 0 && Value < 65536; return Value >= 0 && Value < 65536;
} }
bool isImm24bit() const { bool isImm24bit() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -585,7 +585,7 @@ public:
return Value >= 0 && Value <= 0xffffff; return Value >= 0 && Value <= 0xffffff;
} }
bool isImmThumbSR() const { bool isImmThumbSR() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -593,7 +593,7 @@ public:
return Value > 0 && Value < 33; return Value > 0 && Value < 33;
} }
bool isPKHLSLImm() const { bool isPKHLSLImm() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -601,7 +601,7 @@ public:
return Value >= 0 && Value < 32; return Value >= 0 && Value < 32;
} }
bool isPKHASRImm() const { bool isPKHASRImm() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -609,7 +609,7 @@ public:
return Value > 0 && Value <= 32; return Value > 0 && Value <= 32;
} }
bool isARMSOImm() const { bool isARMSOImm() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -617,7 +617,7 @@ public:
return ARM_AM::getSOImmVal(Value) != -1; return ARM_AM::getSOImmVal(Value) != -1;
} }
bool isT2SOImm() const { bool isT2SOImm() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -625,37 +625,37 @@ public:
return ARM_AM::getT2SOImmVal(Value) != -1; return ARM_AM::getT2SOImmVal(Value) != -1;
} }
bool isSetEndImm() const { bool isSetEndImm() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
int64_t Value = CE->getValue(); int64_t Value = CE->getValue();
return Value == 1 || Value == 0; return Value == 1 || Value == 0;
} }
bool isReg() const { return Kind == Register; } bool isReg() const { return Kind == k_Register; }
bool isRegList() const { return Kind == RegisterList; } bool isRegList() const { return Kind == k_RegisterList; }
bool isDPRRegList() const { return Kind == DPRRegisterList; } bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
bool isSPRRegList() const { return Kind == SPRRegisterList; } bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
bool isToken() const { return Kind == Token; } bool isToken() const { return Kind == k_Token; }
bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; } bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
bool isMemory() const { return Kind == Memory; } bool isMemory() const { return Kind == k_Memory; }
bool isShifterImm() const { return Kind == ShifterImmediate; } bool isShifterImm() const { return Kind == k_ShifterImmediate; }
bool isRegShiftedReg() const { return Kind == ShiftedRegister; } bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
bool isRegShiftedImm() const { return Kind == ShiftedImmediate; } bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
bool isRotImm() const { return Kind == RotateImmediate; } bool isRotImm() const { return Kind == k_RotateImmediate; }
bool isBitfield() const { return Kind == BitfieldDescriptor; } bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; } bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
bool isPostIdxReg() const { bool isPostIdxReg() const {
return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift; return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
} }
bool isMemNoOffset() const { bool isMemNoOffset() const {
if (Kind != Memory) if (Kind != k_Memory)
return false; return false;
// No offset of any kind. // No offset of any kind.
return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0; return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
} }
bool isAddrMode2() const { bool isAddrMode2() const {
if (Kind != Memory) if (Kind != k_Memory)
return false; return false;
// Check for register offset. // Check for register offset.
if (Mem.OffsetRegNum) return true; if (Mem.OffsetRegNum) return true;
@ -665,7 +665,7 @@ public:
return Val > -4096 && Val < 4096; return Val > -4096 && Val < 4096;
} }
bool isAM2OffsetImm() const { bool isAM2OffsetImm() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
// Immediate offset in range [-4095, 4095]. // Immediate offset in range [-4095, 4095].
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
@ -674,7 +674,7 @@ public:
return Val > -4096 && Val < 4096; return Val > -4096 && Val < 4096;
} }
bool isAddrMode3() const { bool isAddrMode3() const {
if (Kind != Memory) if (Kind != k_Memory)
return false; return false;
// No shifts are legal for AM3. // No shifts are legal for AM3.
if (Mem.ShiftType != ARM_AM::no_shift) return false; if (Mem.ShiftType != ARM_AM::no_shift) return false;
@ -686,9 +686,9 @@ public:
return Val > -256 && Val < 256; return Val > -256 && Val < 256;
} }
bool isAM3Offset() const { bool isAM3Offset() const {
if (Kind != Immediate && Kind != PostIndexRegister) if (Kind != k_Immediate && Kind != k_PostIndexRegister)
return false; return false;
if (Kind == PostIndexRegister) if (Kind == k_PostIndexRegister)
return PostIdxReg.ShiftTy == ARM_AM::no_shift; return PostIdxReg.ShiftTy == ARM_AM::no_shift;
// Immediate offset in range [-255, 255]. // Immediate offset in range [-255, 255].
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
@ -698,7 +698,7 @@ public:
return (Val > -256 && Val < 256) || Val == INT32_MIN; return (Val > -256 && Val < 256) || Val == INT32_MIN;
} }
bool isAddrMode5() const { bool isAddrMode5() const {
if (Kind != Memory) if (Kind != k_Memory)
return false; return false;
// Check for register offset. // Check for register offset.
if (Mem.OffsetRegNum) return false; if (Mem.OffsetRegNum) return false;
@ -709,24 +709,24 @@ public:
Val == INT32_MIN; Val == INT32_MIN;
} }
bool isMemTBB() const { bool isMemTBB() const {
if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative || if (Kind != k_Memory || !Mem.OffsetRegNum || Mem.isNegative ||
Mem.ShiftType != ARM_AM::no_shift) Mem.ShiftType != ARM_AM::no_shift)
return false; return false;
return true; return true;
} }
bool isMemTBH() const { bool isMemTBH() const {
if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative || if (Kind != k_Memory || !Mem.OffsetRegNum || Mem.isNegative ||
Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm != 1) Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm != 1)
return false; return false;
return true; return true;
} }
bool isMemRegOffset() const { bool isMemRegOffset() const {
if (Kind != Memory || !Mem.OffsetRegNum) if (Kind != k_Memory || !Mem.OffsetRegNum)
return false; return false;
return true; return true;
} }
bool isT2MemRegOffset() const { bool isT2MemRegOffset() const {
if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative) if (Kind != k_Memory || !Mem.OffsetRegNum || Mem.isNegative)
return false; return false;
// Only lsl #{0, 1, 2, 3} allowed. // Only lsl #{0, 1, 2, 3} allowed.
if (Mem.ShiftType == ARM_AM::no_shift) if (Mem.ShiftType == ARM_AM::no_shift)
@ -738,14 +738,14 @@ public:
bool isMemThumbRR() const { bool isMemThumbRR() const {
// Thumb reg+reg addressing is simple. Just two registers, a base and // Thumb reg+reg addressing is simple. Just two registers, a base and
// an offset. No shifts, negations or any other complicating factors. // an offset. No shifts, negations or any other complicating factors.
if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative || if (Kind != k_Memory || !Mem.OffsetRegNum || Mem.isNegative ||
Mem.ShiftType != ARM_AM::no_shift) Mem.ShiftType != ARM_AM::no_shift)
return false; return false;
return isARMLowRegister(Mem.BaseRegNum) && return isARMLowRegister(Mem.BaseRegNum) &&
(!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum)); (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
} }
bool isMemThumbRIs4() const { bool isMemThumbRIs4() const {
if (Kind != Memory || Mem.OffsetRegNum != 0 || if (Kind != k_Memory || Mem.OffsetRegNum != 0 ||
!isARMLowRegister(Mem.BaseRegNum)) !isARMLowRegister(Mem.BaseRegNum))
return false; return false;
// Immediate offset, multiple of 4 in range [0, 124]. // Immediate offset, multiple of 4 in range [0, 124].
@ -754,7 +754,7 @@ public:
return Val >= 0 && Val <= 124 && (Val % 4) == 0; return Val >= 0 && Val <= 124 && (Val % 4) == 0;
} }
bool isMemThumbRIs2() const { bool isMemThumbRIs2() const {
if (Kind != Memory || Mem.OffsetRegNum != 0 || if (Kind != k_Memory || Mem.OffsetRegNum != 0 ||
!isARMLowRegister(Mem.BaseRegNum)) !isARMLowRegister(Mem.BaseRegNum))
return false; return false;
// Immediate offset, multiple of 4 in range [0, 62]. // Immediate offset, multiple of 4 in range [0, 62].
@ -763,7 +763,7 @@ public:
return Val >= 0 && Val <= 62 && (Val % 2) == 0; return Val >= 0 && Val <= 62 && (Val % 2) == 0;
} }
bool isMemThumbRIs1() const { bool isMemThumbRIs1() const {
if (Kind != Memory || Mem.OffsetRegNum != 0 || if (Kind != k_Memory || Mem.OffsetRegNum != 0 ||
!isARMLowRegister(Mem.BaseRegNum)) !isARMLowRegister(Mem.BaseRegNum))
return false; return false;
// Immediate offset in range [0, 31]. // Immediate offset in range [0, 31].
@ -772,7 +772,7 @@ public:
return Val >= 0 && Val <= 31; return Val >= 0 && Val <= 31;
} }
bool isMemThumbSPI() const { bool isMemThumbSPI() const {
if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP) if (Kind != k_Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
return false; return false;
// Immediate offset, multiple of 4 in range [0, 1020]. // Immediate offset, multiple of 4 in range [0, 1020].
if (!Mem.OffsetImm) return true; if (!Mem.OffsetImm) return true;
@ -780,7 +780,7 @@ public:
return Val >= 0 && Val <= 1020 && (Val % 4) == 0; return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
} }
bool isMemImm8s4Offset() const { bool isMemImm8s4Offset() const {
if (Kind != Memory || Mem.OffsetRegNum != 0) if (Kind != k_Memory || Mem.OffsetRegNum != 0)
return false; return false;
// Immediate offset a multiple of 4 in range [-1020, 1020]. // Immediate offset a multiple of 4 in range [-1020, 1020].
if (!Mem.OffsetImm) return true; if (!Mem.OffsetImm) return true;
@ -788,7 +788,7 @@ public:
return Val >= -1020 && Val <= 1020 && (Val & 3) == 0; return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
} }
bool isMemImm0_1020s4Offset() const { bool isMemImm0_1020s4Offset() const {
if (Kind != Memory || Mem.OffsetRegNum != 0) if (Kind != k_Memory || Mem.OffsetRegNum != 0)
return false; return false;
// Immediate offset a multiple of 4 in range [0, 1020]. // Immediate offset a multiple of 4 in range [0, 1020].
if (!Mem.OffsetImm) return true; if (!Mem.OffsetImm) return true;
@ -796,7 +796,7 @@ public:
return Val >= 0 && Val <= 1020 && (Val & 3) == 0; return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
} }
bool isMemImm8Offset() const { bool isMemImm8Offset() const {
if (Kind != Memory || Mem.OffsetRegNum != 0) if (Kind != k_Memory || Mem.OffsetRegNum != 0)
return false; return false;
// Immediate offset in range [-255, 255]. // Immediate offset in range [-255, 255].
if (!Mem.OffsetImm) return true; if (!Mem.OffsetImm) return true;
@ -804,7 +804,7 @@ public:
return (Val == INT32_MIN) || (Val > -256 && Val < 256); return (Val == INT32_MIN) || (Val > -256 && Val < 256);
} }
bool isMemPosImm8Offset() const { bool isMemPosImm8Offset() const {
if (Kind != Memory || Mem.OffsetRegNum != 0) if (Kind != k_Memory || Mem.OffsetRegNum != 0)
return false; return false;
// Immediate offset in range [0, 255]. // Immediate offset in range [0, 255].
if (!Mem.OffsetImm) return true; if (!Mem.OffsetImm) return true;
@ -812,7 +812,7 @@ public:
return Val >= 0 && Val < 256; return Val >= 0 && Val < 256;
} }
bool isMemNegImm8Offset() const { bool isMemNegImm8Offset() const {
if (Kind != Memory || Mem.OffsetRegNum != 0) if (Kind != k_Memory || Mem.OffsetRegNum != 0)
return false; return false;
// Immediate offset in range [-255, -1]. // Immediate offset in range [-255, -1].
if (!Mem.OffsetImm) return true; if (!Mem.OffsetImm) return true;
@ -823,10 +823,10 @@ public:
// If we have an immediate that's not a constant, treat it as a label // If we have an immediate that's not a constant, treat it as a label
// reference needing a fixup. If it is a constant, it's something else // reference needing a fixup. If it is a constant, it's something else
// and we reject it. // and we reject it.
if (Kind == Immediate && !isa<MCConstantExpr>(getImm())) if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
return true; return true;
if (Kind != Memory || Mem.OffsetRegNum != 0) if (Kind != k_Memory || Mem.OffsetRegNum != 0)
return false; return false;
// Immediate offset in range [0, 4095]. // Immediate offset in range [0, 4095].
if (!Mem.OffsetImm) return true; if (!Mem.OffsetImm) return true;
@ -837,10 +837,10 @@ public:
// If we have an immediate that's not a constant, treat it as a label // If we have an immediate that's not a constant, treat it as a label
// reference needing a fixup. If it is a constant, it's something else // reference needing a fixup. If it is a constant, it's something else
// and we reject it. // and we reject it.
if (Kind == Immediate && !isa<MCConstantExpr>(getImm())) if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
return true; return true;
if (Kind != Memory || Mem.OffsetRegNum != 0) if (Kind != k_Memory || Mem.OffsetRegNum != 0)
return false; return false;
// Immediate offset in range [-4095, 4095]. // Immediate offset in range [-4095, 4095].
if (!Mem.OffsetImm) return true; if (!Mem.OffsetImm) return true;
@ -848,7 +848,7 @@ public:
return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
} }
bool isPostIdxImm8() const { bool isPostIdxImm8() const {
if (Kind != Immediate) if (Kind != k_Immediate)
return false; return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false; if (!CE) return false;
@ -856,8 +856,8 @@ public:
return (Val > -256 && Val < 256) || (Val == INT32_MIN); return (Val > -256 && Val < 256) || (Val == INT32_MIN);
} }
bool isMSRMask() const { return Kind == MSRMask; } bool isMSRMask() const { return Kind == k_MSRMask; }
bool isProcIFlags() const { return Kind == ProcIFlags; } bool isProcIFlags() const { return Kind == k_ProcIFlags; }
void addExpr(MCInst &Inst, const MCExpr *Expr) const { void addExpr(MCInst &Inst, const MCExpr *Expr) const {
// Add as immediates when possible. Null MCExpr = 0. // Add as immediates when possible. Null MCExpr = 0.
@ -1150,7 +1150,7 @@ public:
void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!"); assert(N == 2 && "Invalid number of operands!");
if (Kind == PostIndexRegister) { if (Kind == k_PostIndexRegister) {
int32_t Val = int32_t Val =
ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
@ -1216,7 +1216,7 @@ public:
void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!"); assert(N == 2 && "Invalid number of operands!");
// If this is an immediate, it's a label reference. // If this is an immediate, it's a label reference.
if (Kind == Immediate) { if (Kind == k_Immediate) {
addExpr(Inst, getImm()); addExpr(Inst, getImm());
Inst.addOperand(MCOperand::CreateImm(0)); Inst.addOperand(MCOperand::CreateImm(0));
return; return;
@ -1231,7 +1231,7 @@ public:
void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!"); assert(N == 2 && "Invalid number of operands!");
// If this is an immediate, it's a label reference. // If this is an immediate, it's a label reference.
if (Kind == Immediate) { if (Kind == k_Immediate) {
addExpr(Inst, getImm()); addExpr(Inst, getImm());
Inst.addOperand(MCOperand::CreateImm(0)); Inst.addOperand(MCOperand::CreateImm(0));
return; return;
@ -1346,7 +1346,7 @@ public:
virtual void print(raw_ostream &OS) const; virtual void print(raw_ostream &OS) const;
static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
ARMOperand *Op = new ARMOperand(ITCondMask); ARMOperand *Op = new ARMOperand(k_ITCondMask);
Op->ITMask.Mask = Mask; Op->ITMask.Mask = Mask;
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = S; Op->EndLoc = S;
@ -1354,7 +1354,7 @@ public:
} }
static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
ARMOperand *Op = new ARMOperand(CondCode); ARMOperand *Op = new ARMOperand(k_CondCode);
Op->CC.Val = CC; Op->CC.Val = CC;
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = S; Op->EndLoc = S;
@ -1362,7 +1362,7 @@ public:
} }
static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
ARMOperand *Op = new ARMOperand(CoprocNum); ARMOperand *Op = new ARMOperand(k_CoprocNum);
Op->Cop.Val = CopVal; Op->Cop.Val = CopVal;
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = S; Op->EndLoc = S;
@ -1370,7 +1370,7 @@ public:
} }
static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
ARMOperand *Op = new ARMOperand(CoprocReg); ARMOperand *Op = new ARMOperand(k_CoprocReg);
Op->Cop.Val = CopVal; Op->Cop.Val = CopVal;
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = S; Op->EndLoc = S;
@ -1378,7 +1378,7 @@ public:
} }
static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
ARMOperand *Op = new ARMOperand(CCOut); ARMOperand *Op = new ARMOperand(k_CCOut);
Op->Reg.RegNum = RegNum; Op->Reg.RegNum = RegNum;
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = S; Op->EndLoc = S;
@ -1386,7 +1386,7 @@ public:
} }
static ARMOperand *CreateToken(StringRef Str, SMLoc S) { static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
ARMOperand *Op = new ARMOperand(Token); ARMOperand *Op = new ARMOperand(k_Token);
Op->Tok.Data = Str.data(); Op->Tok.Data = Str.data();
Op->Tok.Length = Str.size(); Op->Tok.Length = Str.size();
Op->StartLoc = S; Op->StartLoc = S;
@ -1395,7 +1395,7 @@ public:
} }
static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(Register); ARMOperand *Op = new ARMOperand(k_Register);
Op->Reg.RegNum = RegNum; Op->Reg.RegNum = RegNum;
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = E; Op->EndLoc = E;
@ -1407,7 +1407,7 @@ public:
unsigned ShiftReg, unsigned ShiftReg,
unsigned ShiftImm, unsigned ShiftImm,
SMLoc S, SMLoc E) { SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(ShiftedRegister); ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
Op->RegShiftedReg.ShiftTy = ShTy; Op->RegShiftedReg.ShiftTy = ShTy;
Op->RegShiftedReg.SrcReg = SrcReg; Op->RegShiftedReg.SrcReg = SrcReg;
Op->RegShiftedReg.ShiftReg = ShiftReg; Op->RegShiftedReg.ShiftReg = ShiftReg;
@ -1421,7 +1421,7 @@ public:
unsigned SrcReg, unsigned SrcReg,
unsigned ShiftImm, unsigned ShiftImm,
SMLoc S, SMLoc E) { SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(ShiftedImmediate); ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
Op->RegShiftedImm.ShiftTy = ShTy; Op->RegShiftedImm.ShiftTy = ShTy;
Op->RegShiftedImm.SrcReg = SrcReg; Op->RegShiftedImm.SrcReg = SrcReg;
Op->RegShiftedImm.ShiftImm = ShiftImm; Op->RegShiftedImm.ShiftImm = ShiftImm;
@ -1432,7 +1432,7 @@ public:
static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
SMLoc S, SMLoc E) { SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(ShifterImmediate); ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
Op->ShifterImm.isASR = isASR; Op->ShifterImm.isASR = isASR;
Op->ShifterImm.Imm = Imm; Op->ShifterImm.Imm = Imm;
Op->StartLoc = S; Op->StartLoc = S;
@ -1441,7 +1441,7 @@ public:
} }
static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(RotateImmediate); ARMOperand *Op = new ARMOperand(k_RotateImmediate);
Op->RotImm.Imm = Imm; Op->RotImm.Imm = Imm;
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = E; Op->EndLoc = E;
@ -1450,7 +1450,7 @@ public:
static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
SMLoc S, SMLoc E) { SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(BitfieldDescriptor); ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
Op->Bitfield.LSB = LSB; Op->Bitfield.LSB = LSB;
Op->Bitfield.Width = Width; Op->Bitfield.Width = Width;
Op->StartLoc = S; Op->StartLoc = S;
@ -1461,13 +1461,13 @@ public:
static ARMOperand * static ARMOperand *
CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
SMLoc StartLoc, SMLoc EndLoc) { SMLoc StartLoc, SMLoc EndLoc) {
KindTy Kind = RegisterList; KindTy Kind = k_RegisterList;
if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
Kind = DPRRegisterList; Kind = k_DPRRegisterList;
else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
contains(Regs.front().first)) contains(Regs.front().first))
Kind = SPRRegisterList; Kind = k_SPRRegisterList;
ARMOperand *Op = new ARMOperand(Kind); ARMOperand *Op = new ARMOperand(Kind);
for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
@ -1480,7 +1480,7 @@ public:
} }
static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(Immediate); ARMOperand *Op = new ARMOperand(k_Immediate);
Op->Imm.Val = Val; Op->Imm.Val = Val;
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = E; Op->EndLoc = E;
@ -1488,7 +1488,7 @@ public:
} }
static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) { static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
ARMOperand *Op = new ARMOperand(FPImmediate); ARMOperand *Op = new ARMOperand(k_FPImmediate);
Op->FPImm.Val = Val; Op->FPImm.Val = Val;
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = S; Op->EndLoc = S;
@ -1502,7 +1502,7 @@ public:
unsigned ShiftImm, unsigned ShiftImm,
bool isNegative, bool isNegative,
SMLoc S, SMLoc E) { SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(Memory); ARMOperand *Op = new ARMOperand(k_Memory);
Op->Mem.BaseRegNum = BaseRegNum; Op->Mem.BaseRegNum = BaseRegNum;
Op->Mem.OffsetImm = OffsetImm; Op->Mem.OffsetImm = OffsetImm;
Op->Mem.OffsetRegNum = OffsetRegNum; Op->Mem.OffsetRegNum = OffsetRegNum;
@ -1518,7 +1518,7 @@ public:
ARM_AM::ShiftOpc ShiftTy, ARM_AM::ShiftOpc ShiftTy,
unsigned ShiftImm, unsigned ShiftImm,
SMLoc S, SMLoc E) { SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(PostIndexRegister); ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
Op->PostIdxReg.RegNum = RegNum; Op->PostIdxReg.RegNum = RegNum;
Op->PostIdxReg.isAdd = isAdd; Op->PostIdxReg.isAdd = isAdd;
Op->PostIdxReg.ShiftTy = ShiftTy; Op->PostIdxReg.ShiftTy = ShiftTy;
@ -1529,7 +1529,7 @@ public:
} }
static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
ARMOperand *Op = new ARMOperand(MemBarrierOpt); ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
Op->MBOpt.Val = Opt; Op->MBOpt.Val = Opt;
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = S; Op->EndLoc = S;
@ -1537,7 +1537,7 @@ public:
} }
static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
ARMOperand *Op = new ARMOperand(ProcIFlags); ARMOperand *Op = new ARMOperand(k_ProcIFlags);
Op->IFlags.Val = IFlags; Op->IFlags.Val = IFlags;
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = S; Op->EndLoc = S;
@ -1545,7 +1545,7 @@ public:
} }
static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
ARMOperand *Op = new ARMOperand(MSRMask); ARMOperand *Op = new ARMOperand(k_MSRMask);
Op->MMask.Val = MMask; Op->MMask.Val = MMask;
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = S; Op->EndLoc = S;
@ -1557,17 +1557,17 @@ public:
void ARMOperand::print(raw_ostream &OS) const { void ARMOperand::print(raw_ostream &OS) const {
switch (Kind) { switch (Kind) {
case FPImmediate: case k_FPImmediate:
OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm()) OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
<< ") >"; << ") >";
break; break;
case CondCode: case k_CondCode:
OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
break; break;
case CCOut: case k_CCOut:
OS << "<ccout " << getReg() << ">"; OS << "<ccout " << getReg() << ">";
break; break;
case ITCondMask: { case k_ITCondMask: {
static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)", static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
"(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)", "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
"(tee)", "(eee)" }; "(tee)", "(eee)" };
@ -1575,27 +1575,27 @@ void ARMOperand::print(raw_ostream &OS) const {
OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
break; break;
} }
case CoprocNum: case k_CoprocNum:
OS << "<coprocessor number: " << getCoproc() << ">"; OS << "<coprocessor number: " << getCoproc() << ">";
break; break;
case CoprocReg: case k_CoprocReg:
OS << "<coprocessor register: " << getCoproc() << ">"; OS << "<coprocessor register: " << getCoproc() << ">";
break; break;
case MSRMask: case k_MSRMask:
OS << "<mask: " << getMSRMask() << ">"; OS << "<mask: " << getMSRMask() << ">";
break; break;
case Immediate: case k_Immediate:
getImm()->print(OS); getImm()->print(OS);
break; break;
case MemBarrierOpt: case k_MemBarrierOpt:
OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
break; break;
case Memory: case k_Memory:
OS << "<memory " OS << "<memory "
<< " base:" << Mem.BaseRegNum; << " base:" << Mem.BaseRegNum;
OS << ">"; OS << ">";
break; break;
case PostIndexRegister: case k_PostIndexRegister:
OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
<< PostIdxReg.RegNum; << PostIdxReg.RegNum;
if (PostIdxReg.ShiftTy != ARM_AM::no_shift) if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
@ -1603,7 +1603,7 @@ void ARMOperand::print(raw_ostream &OS) const {
<< PostIdxReg.ShiftImm; << PostIdxReg.ShiftImm;
OS << ">"; OS << ">";
break; break;
case ProcIFlags: { case k_ProcIFlags: {
OS << "<ARM_PROC::"; OS << "<ARM_PROC::";
unsigned IFlags = getProcIFlags(); unsigned IFlags = getProcIFlags();
for (int i=2; i >= 0; --i) for (int i=2; i >= 0; --i)
@ -1612,14 +1612,14 @@ void ARMOperand::print(raw_ostream &OS) const {
OS << ">"; OS << ">";
break; break;
} }
case Register: case k_Register:
OS << "<register " << getReg() << ">"; OS << "<register " << getReg() << ">";
break; break;
case ShifterImmediate: case k_ShifterImmediate:
OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
<< " #" << ShifterImm.Imm << ">"; << " #" << ShifterImm.Imm << ">";
break; break;
case ShiftedRegister: case k_ShiftedRegister:
OS << "<so_reg_reg " OS << "<so_reg_reg "
<< RegShiftedReg.SrcReg << RegShiftedReg.SrcReg
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm)) << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
@ -1627,23 +1627,23 @@ void ARMOperand::print(raw_ostream &OS) const {
<< ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm) << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
<< ">"; << ">";
break; break;
case ShiftedImmediate: case k_ShiftedImmediate:
OS << "<so_reg_imm " OS << "<so_reg_imm "
<< RegShiftedImm.SrcReg << RegShiftedImm.SrcReg
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm)) << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
<< ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm) << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
<< ">"; << ">";
break; break;
case RotateImmediate: case k_RotateImmediate:
OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
break; break;
case BitfieldDescriptor: case k_BitfieldDescriptor:
OS << "<bitfield " << "lsb: " << Bitfield.LSB OS << "<bitfield " << "lsb: " << Bitfield.LSB
<< ", width: " << Bitfield.Width << ">"; << ", width: " << Bitfield.Width << ">";
break; break;
case RegisterList: case k_RegisterList:
case DPRRegisterList: case k_DPRRegisterList:
case SPRRegisterList: { case k_SPRRegisterList: {
OS << "<register_list "; OS << "<register_list ";
const SmallVectorImpl<unsigned> &RegList = getRegList(); const SmallVectorImpl<unsigned> &RegList = getRegList();
@ -1656,7 +1656,7 @@ void ARMOperand::print(raw_ostream &OS) const {
OS << ">"; OS << ">";
break; break;
} }
case Token: case k_Token:
OS << "'" << getToken() << "'"; OS << "'" << getToken() << "'";
break; break;
} }
@ -3640,8 +3640,8 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
// ARM mode 'blx' need special handling, as the register operand version // ARM mode 'blx' need special handling, as the register operand version
// is predicable, but the label operand version is not. So, we can't rely // is predicable, but the label operand version is not. So, we can't rely
// on the Mnemonic based checking to correctly figure out when to put // on the Mnemonic based checking to correctly figure out when to put
// a CondCode operand in the list. If we're trying to match the label // a k_CondCode operand in the list. If we're trying to match the label
// version, remove the CondCode operand here. // version, remove the k_CondCode operand here.
if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
static_cast<ARMOperand*>(Operands[2])->isImm()) { static_cast<ARMOperand*>(Operands[2])->isImm()) {
ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);