From 22274378d5ec800c08246d179ea003a5c85d3cb9 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 6 Feb 2014 18:36:34 +0000 Subject: [PATCH] R600/SI: Use immediates offsets for SMRD instructions whenever possible There was a problem with the old pattern, so we were copying some larger immediates into registers when we could have been encoding them in the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200932 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIInstrInfo.td | 17 ++++--- lib/Target/R600/SIInstructions.td | 6 +-- test/CodeGen/R600/smrd.ll | 80 +++++++++++++++++++++++++++++++ 3 files changed, 93 insertions(+), 10 deletions(-) create mode 100644 test/CodeGen/R600/smrd.ll diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 97d37d894ab..871509f1942 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -75,15 +75,14 @@ def HI32f : SDNodeXFormgetTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32); }]>; -def IMM8bitDWORD : ImmLeaf < - i32, [{ - return (Imm & ~0x3FC) == 0; - }], SDNodeXFormgetTargetConstant( - N->getZExtValue() >> 2, MVT::i32); - }]> +def IMM8bitDWORD : PatLeaf <(imm), + [{return (N->getZExtValue() & ~0x3FC) == 0;}] >; +def as_dword_i32imm : SDNodeXFormgetTargetConstant(N->getZExtValue() >> 2, MVT::i32); +}]>; + def as_i1imm : SDNodeXFormgetTargetConstant(N->getZExtValue(), MVT::i1); }]>; @@ -96,6 +95,10 @@ def as_i16imm : SDNodeXFormgetTargetConstant(N->getSExtValue(), MVT::i16); }]>; +def as_i32imm: SDNodeXFormgetTargetConstant(N->getSExtValue(), MVT::i32); +}]>; + def IMM12bit : PatLeaf <(imm), [{return isUInt<12>(N->getZExtValue());}] >; diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 25fd7d50508..d00deba0d48 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1846,7 +1846,7 @@ def : Pat < // 1. Offset as 8bit DWORD immediate def : Pat < (SIload_constant i128:$sbase, IMM8bitDWORD:$offset), - (S_BUFFER_LOAD_DWORD_IMM $sbase, IMM8bitDWORD:$offset) + (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset)) >; // 2. Offset loaded in an 32bit SGPR @@ -1926,8 +1926,8 @@ multiclass SMRD_Pattern { // 1. Offset as 8bit DWORD immediate def : Pat < - (constant_load (SIadd64bit32bit i64:$sbase, IMM8bitDWORD:$offset)), - (vt (Instr_IMM $sbase, IMM8bitDWORD:$offset)) + (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))), + (vt (Instr_IMM $sbase, (as_dword_i32imm $offset))) >; // 2. Offset loaded in an 32bit SGPR diff --git a/test/CodeGen/R600/smrd.ll b/test/CodeGen/R600/smrd.ll new file mode 100644 index 00000000000..43231df4adc --- /dev/null +++ b/test/CodeGen/R600/smrd.ll @@ -0,0 +1,80 @@ +; RUN: llc < %s -march=r600 -mcpu=SI -show-mc-encoding -verify-machineinstrs | FileCheck %s + +; SMRD load with an immediate offset. +; CHECK-LABEL: @smrd0 +; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 1 ; encoding: [0x01 +define void @smrd0(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { +entry: + %0 = getelementptr i32 addrspace(2)* %ptr, i64 1 + %1 = load i32 addrspace(2)* %0 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; SMRD load with the largest possible immediate offset. +; CHECK-LABEL: @smrd1 +; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 255 ; encoding: [0xff +define void @smrd1(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { +entry: + %0 = getelementptr i32 addrspace(2)* %ptr, i64 255 + %1 = load i32 addrspace(2)* %0 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; SMRD load with an offset greater than the largest possible immediate. +; CHECK-LABEL: @smrd2 +; CHECK: S_MOV_B32 s[[OFFSET:[0-9]]], 1024 +; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] +define void @smrd2(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { +entry: + %0 = getelementptr i32 addrspace(2)* %ptr, i64 256 + %1 = load i32 addrspace(2)* %0 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; SMRD load using the load.const intrinsic with an immediate offset +; CHECK-LABEL: @smrd_load_const0 +; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 4 ; encoding: [0x04 +define void @smrd_load_const0(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +main_body: + %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0 + %21 = load <16 x i8> addrspace(2)* %20 + %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16) + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22) + ret void +} + +; SMRD load using the load.const intrinsic with an offset greater largest possible +; immediate offset. +; CHECK-LABEL: @smrd_load_const1 +; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 255 ; encoding: [0xff +define void @smrd_load_const1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +main_body: + %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0 + %21 = load <16 x i8> addrspace(2)* %20 + %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1020) + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22) + ret void +} +; SMRD load using the load.const intrinsic with the largetst possible +; immediate offset. +; CHECK-LABEL: @smrd_load_const2 +; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] +define void @smrd_load_const2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +main_body: + %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0 + %21 = load <16 x i8> addrspace(2)* %20 + %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1024) + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22) + ret void +} + +; Function Attrs: nounwind readnone +declare float @llvm.SI.load.const(<16 x i8>, i32) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { nounwind readnone }