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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-20 14:29:27 +00:00
Pull out setcc, this reduces stack frame size from 7520 to 6032 bytes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23649 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
2b63e4c5e2
commit
222adac30a
@ -93,9 +93,10 @@ namespace {
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#include "PPC32GenDAGISel.inc"
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private:
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SDOperand SelectDYNAMIC_STACKALLOC(SDOperand N);
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SDOperand SelectADD_PARTS(SDOperand N);
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SDOperand SelectSUB_PARTS(SDOperand N);
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SDOperand SelectDYNAMIC_STACKALLOC(SDOperand Op);
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SDOperand SelectADD_PARTS(SDOperand Op);
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SDOperand SelectSUB_PARTS(SDOperand Op);
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SDOperand SelectSETCC(SDOperand Op);
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};
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}
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@ -775,6 +776,113 @@ SDOperand PPC32DAGToDAGISel::SelectSUB_PARTS(SDOperand Op) {
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return Result[Op.ResNo];
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}
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SDOperand PPC32DAGToDAGISel::SelectSETCC(SDOperand Op) {
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SDNode *N = Op.Val;
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unsigned Imm;
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
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if (isIntImmediate(N->getOperand(1), Imm)) {
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// We can codegen setcc op, imm very efficiently compared to a brcond.
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// Check for those cases here.
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// setcc op, 0
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if (Imm == 0) {
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SDOperand Op = Select(N->getOperand(0));
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switch (CC) {
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default: assert(0 && "Unhandled SetCC condition"); abort();
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case ISD::SETEQ:
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Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
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getI32Imm(5), getI32Imm(31));
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break;
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case ISD::SETNE: {
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SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
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Op, getI32Imm(~0U));
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CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
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break;
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}
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case ISD::SETLT:
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
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getI32Imm(31), getI32Imm(31));
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break;
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case ISD::SETGT: {
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SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
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T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
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getI32Imm(31), getI32Imm(31));
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break;
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}
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}
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return SDOperand(N, 0);
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} else if (Imm == ~0U) { // setcc op, -1
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SDOperand Op = Select(N->getOperand(0));
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switch (CC) {
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default: assert(0 && "Unhandled SetCC condition"); abort();
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case ISD::SETEQ:
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Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
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Op, getI32Imm(1));
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CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
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CurDAG->getTargetNode(PPC::LI, MVT::i32,
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getI32Imm(0)),
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Op.getValue(1));
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break;
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case ISD::SETNE: {
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Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
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SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
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Op, getI32Imm(~0U));
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CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
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break;
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}
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case ISD::SETLT: {
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SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
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getI32Imm(1));
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SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
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getI32Imm(31), getI32Imm(31));
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break;
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}
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case ISD::SETGT:
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Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
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getI32Imm(31), getI32Imm(31));
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CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
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break;
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}
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return SDOperand(N, 0);
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}
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}
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bool Inv;
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unsigned Idx = getCRIdxForSetCC(CC, Inv);
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SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
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SDOperand IntCR;
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// Force the ccreg into CR7.
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SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
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std::vector<MVT::ValueType> VTs;
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VTs.push_back(MVT::Other);
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VTs.push_back(MVT::Flag); // NONSTANDARD CopyToReg node: defines a flag
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std::vector<SDOperand> Ops;
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Ops.push_back(CurDAG->getEntryNode());
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Ops.push_back(CR7Reg);
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Ops.push_back(CCReg);
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CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1);
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if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
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IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
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else
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IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
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if (!Inv) {
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
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getI32Imm(32-(3-Idx)), getI32Imm(31), getI32Imm(31));
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} else {
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SDOperand Tmp =
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CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
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getI32Imm(32-(3-Idx)), getI32Imm(31),getI32Imm(31));
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CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
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}
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return SDOperand(N, 0);
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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@ -790,6 +898,10 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::DYNAMIC_STACKALLOC: return SelectDYNAMIC_STACKALLOC(Op);
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case ISD::ADD_PARTS: return SelectADD_PARTS(Op);
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case ISD::SUB_PARTS: return SelectSUB_PARTS(Op);
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case ISD::SETCC: return SelectSETCC(Op);
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case ISD::TokenFactor: {
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SDOperand New;
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if (N->getNumOperands() == 2) {
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@ -862,8 +974,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, GA);
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return SDOperand(N, 0);
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}
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case ISD::DYNAMIC_STACKALLOC:
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return SelectDYNAMIC_STACKALLOC(Op);
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case PPCISD::FSEL: {
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SDOperand Comparison = Select(N->getOperand(0));
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// Extend the comparison to 64-bits.
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@ -1132,9 +1243,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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Select(N->getOperand(0)));
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return SDOperand(N, 0);
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}
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case ISD::ADD_PARTS: return SelectADD_PARTS(Op);
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case ISD::SUB_PARTS: return SelectSUB_PARTS(Op);
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case ISD::LOAD:
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case ISD::EXTLOAD:
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case ISD::ZEXTLOAD:
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@ -1209,113 +1318,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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return SDOperand(N, 0);
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}
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case ISD::SETCC: {
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unsigned Imm;
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
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if (isIntImmediate(N->getOperand(1), Imm)) {
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// We can codegen setcc op, imm very efficiently compared to a brcond.
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// Check for those cases here.
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// setcc op, 0
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if (Imm == 0) {
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SDOperand Op = Select(N->getOperand(0));
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switch (CC) {
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default: assert(0 && "Unhandled SetCC condition"); abort();
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case ISD::SETEQ:
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Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
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getI32Imm(5), getI32Imm(31));
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break;
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case ISD::SETNE: {
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SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
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Op, getI32Imm(~0U));
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CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
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break;
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}
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case ISD::SETLT:
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
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getI32Imm(31), getI32Imm(31));
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break;
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case ISD::SETGT: {
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SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
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T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
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getI32Imm(31), getI32Imm(31));
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break;
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}
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}
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return SDOperand(N, 0);
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} else if (Imm == ~0U) { // setcc op, -1
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SDOperand Op = Select(N->getOperand(0));
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switch (CC) {
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default: assert(0 && "Unhandled SetCC condition"); abort();
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case ISD::SETEQ:
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Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
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Op, getI32Imm(1));
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CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
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CurDAG->getTargetNode(PPC::LI, MVT::i32,
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getI32Imm(0)),
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Op.getValue(1));
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break;
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case ISD::SETNE: {
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Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
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SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
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Op, getI32Imm(~0U));
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CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
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break;
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}
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case ISD::SETLT: {
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SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
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getI32Imm(1));
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SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
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getI32Imm(31), getI32Imm(31));
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break;
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}
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case ISD::SETGT:
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Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
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getI32Imm(31), getI32Imm(31));
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CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
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break;
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}
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return SDOperand(N, 0);
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}
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}
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bool Inv;
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unsigned Idx = getCRIdxForSetCC(CC, Inv);
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SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
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SDOperand IntCR;
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// Force the ccreg into CR7.
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SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
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std::vector<MVT::ValueType> VTs;
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VTs.push_back(MVT::Other);
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VTs.push_back(MVT::Flag); // NONSTANDARD CopyToReg node: defines a flag
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std::vector<SDOperand> Ops;
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Ops.push_back(CurDAG->getEntryNode());
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Ops.push_back(CR7Reg);
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Ops.push_back(CCReg);
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CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1);
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if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
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IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
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else
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IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
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if (!Inv) {
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
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getI32Imm(32-(3-Idx)), getI32Imm(31), getI32Imm(31));
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} else {
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SDOperand Tmp =
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CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
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getI32Imm(32-(3-Idx)), getI32Imm(31),getI32Imm(31));
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CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
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}
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return SDOperand(N, 0);
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}
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case ISD::SELECT_CC: {
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
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