6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-10 02:36:06 +00:00
Code Issues Projects Releases Wiki Activity

Remove the code from the scheduler that commuted two-address

Browse Source 
instructions to avoid copies, because TwoAddressInstructionPass
also does this optimization.  The scheduler's version didn't
account for live-out values, which resulted in spurious commutes
and missed opportunities.

Now, TwoAddressInstructionPass handles all the opportunities,
instead of just those that the scheduler missed. The result is
usually the same, though there are occasional trivial differences
resulting from the avoidance of spurious commutes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61611 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-01-03 18:01:46 +00:00
parent 3b3b4e3f0f
commit 223942a420
3 changed files with 0 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
include/llvm/CodeGen/ScheduleDAGSDNodes.h
View File

@ -17,7 +17,6 @@
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/ADT/SmallSet.h"
namespace llvm {
/// HazardRecognizer - This determines whether or not an instruction can be
@ -75,8 +74,6 @@ namespace llvm {
///
class ScheduleDAGSDNodes : public ScheduleDAG {
public:
SmallSet<SDNode*, 16> CommuteSet; // Nodes that should be commuted.
ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb,
const TargetMachine &tm);

54
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -186,60 +186,6 @@ void ScheduleDAGRRList::Schedule() {
ListScheduleTopDown();
AvailableQueue->releaseState();
CommuteNodesToReducePressure();
}
/// CommuteNodesToReducePressure - If a node is two-address and commutable, and
/// it is not the last use of its first operand, add it to the CommuteSet if
/// possible. It will be commuted when it is translated to a MI.
void ScheduleDAGRRList::CommuteNodesToReducePressure() {
SmallPtrSet<SUnit*, 4> OperandSeen;
for (unsigned i = Sequence.size(); i != 0; ) {
--i;
SUnit *SU = Sequence[i];
if (!SU || !SU->getNode()) continue;
if (SU->isCommutable) {
unsigned Opc = SU->getNode()->getMachineOpcode();
const TargetInstrDesc &TID = TII->get(Opc);
unsigned NumRes = TID.getNumDefs();
unsigned NumOps = TID.getNumOperands() - NumRes;
for (unsigned j = 0; j != NumOps; ++j) {
if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
continue;
SDNode *OpN = SU->getNode()->getOperand(j).getNode();
SUnit *OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()];
if (OpSU && OperandSeen.count(OpSU) == 1) {
// Ok, so SU is not the last use of OpSU, but SU is two-address so
// it will clobber OpSU. Try to commute SU if no other source operands
// are live below.
bool DoCommute = true;
for (unsigned k = 0; k < NumOps; ++k) {
if (k != j) {
OpN = SU->getNode()->getOperand(k).getNode();
OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()];
if (OpSU && OperandSeen.count(OpSU) == 1) {
DoCommute = false;
break;
}
}
}
if (DoCommute)
CommuteSet.insert(SU->getNode());
}
// Only look at the first use&def node for now.
break;
}
}
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) {
if (!I->isCtrl())
OperandSeen.insert(I->getSUnit()->OrigNode);
}
}
}
//===----------------------------------------------------------------------===//

17
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
View File

@ -28,8 +28,6 @@
#include "llvm/Support/MathExtras.h"
using namespace llvm;
STATISTIC(NumCommutes, "Number of instructions commuted");
/// getInstrOperandRegClass - Return register class of the operand of an
/// instruction of the specified TargetInstrDesc.
static const TargetRegisterClass*
@ -500,21 +498,6 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone,
for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO);
// Commute node if it has been determined to be profitable.
if (CommuteSet.count(Node)) {
MachineInstr *NewMI = TII->commuteInstruction(MI);
if (NewMI == 0)
DOUT << "Sched: COMMUTING FAILED!\n";
else {
DOUT << "Sched: COMMUTED TO: " << *NewMI;
if (MI != NewMI) {
MF->DeleteMachineInstr(MI);
MI = NewMI;
}
++NumCommutes;
}
}
if (II.usesCustomDAGSchedInsertionHook())
// Insert this instruction into the basic block using a target
// specific inserter which may returns a new basic block.