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[DAGCombiner] Add more rules to fold shuffles.
This patch adds two new rules to the DAGCombiner:
1. shuffle (shuffle A, Undef, M0), B, M1 -> shuffle A, B, M2
2. shuffle (shuffle A, Undef, M0), A, M1 -> shuffle A, Undef, M2
We only do this if the combined shuffle is legal for the target.
Example:
;;
define <4 x float> @test(<4 x float> %a, <4 x float> %b) {
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32><i32 6, i32 0, i32 1, i32 7>
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32><i32 1, i32 2, i32 4, i32 5>
ret <4 x i32> %2
}
;;
(using llc -mcpu=corei7 -march=x86-64)
Before, the x86 backend generated:
pshufd $120, %xmm0, %xmm0
shufps $-108, %xmm0, %xmm1
movaps %xmm1, %xmm0
Now the x86 backend generates:
movsd %xmm1, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213069 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
parent
3ee5fc8618
commit
224ffa2549
@ -10780,11 +10780,13 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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}
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// Try to fold according to rules:
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// shuffle(shuffle A, B, M0), B, M1) -> shuffle(A, B, M2)
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// shuffle(shuffle A, B, M0), A, M1) -> shuffle(A, B, M2)
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// shuffle(shuffle(A, B, M0), B, M1) -> shuffle(A, B, M2)
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// shuffle(shuffle(A, B, M0), A, M1) -> shuffle(A, B, M2)
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// shuffle(shuffle(A, Undef, M0), B, M1) -> shuffle(A, B, M2)
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// shuffle(shuffle(A, Undef, M0), A, M1) -> shuffle(A, Undef, M2)
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// Don't try to fold shuffles with illegal type.
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if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
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TLI.isTypeLegal(VT)) {
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N1.getOpcode() != ISD::UNDEF && TLI.isTypeLegal(VT)) {
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ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
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// The incoming shuffle must be of the same type as the result of the
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@ -10795,7 +10797,8 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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SDValue SV0 = OtherSV->getOperand(0);
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SDValue SV1 = OtherSV->getOperand(1);
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bool HasSameOp0 = N1 == SV0;
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if (!HasSameOp0 && N1 != SV1)
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bool IsSV1Undef = SV1.getOpcode() == ISD::UNDEF;
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if (!HasSameOp0 && !IsSV1Undef && N1 != SV1)
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// Early exit.
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return SDValue();
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@ -10810,17 +10813,24 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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continue;
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}
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if (Idx < (int)NumElts)
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if (Idx < (int)NumElts) {
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Idx = OtherSV->getMaskElt(Idx);
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else
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if (IsSV1Undef && Idx >= (int) NumElts)
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Idx = -1; // Propagate Undef.
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} else
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Idx = HasSameOp0 ? Idx - NumElts : Idx;
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Mask.push_back(Idx);
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}
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// Avoid introducing shuffles with illegal mask.
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if (TLI.isShuffleMaskLegal(Mask, VT))
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if (TLI.isShuffleMaskLegal(Mask, VT)) {
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if (IsSV1Undef)
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// shuffle(shuffle(A, Undef, M0), B, M1) -> shuffle(A, B, M2)
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// shuffle(shuffle(A, Undef, M0), A, M1) -> shuffle(A, Undef, M2)
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return DAG.getVectorShuffle(VT, SDLoc(N), SV0, N1, &Mask[0]);
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return DAG.getVectorShuffle(VT, SDLoc(N), SV0, SV1, &Mask[0]);
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}
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}
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return SDValue();
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122
test/CodeGen/X86/combine-vec-shuffle-4.ll
Normal file
122
test/CodeGen/X86/combine-vec-shuffle-4.ll
Normal file
@ -0,0 +1,122 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
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; Verify that we fold shuffles according to rule:
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; (shuffle(shuffle A, Undef, M0), B, M1) -> (shuffle A, B, M2)
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define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
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%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
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%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test1
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; Mask: [4,5,2,3]
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; CHECK: movsd
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; CHECK: ret
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define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
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%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
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%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test2
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; Mask: [0,1,4,5]
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; CHECK: movlhps
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; CHECK: ret
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define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
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%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
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%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test3
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; Mask: [0,1,4,u]
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; CHECK: movlhps
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; CHECK: ret
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define <4 x float> @test4(<4 x float> %a, <4 x float> %b) {
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%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
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%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
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ret <4 x float> %2
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}
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; FIXME: this should be lowered as a single movhlps. However, the backend
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; wrongly thinks that shuffle mask [6,7,2,3] is not legal. Therefore, we
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; end up with the sub-optimal sequence 'movhlps, palignr'.
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; CHECK-LABEL: test4
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; Mask: [6,7,2,3]
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; CHECK: movhlps
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; CHECK: palignr $8
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; CHECK: ret
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define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
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%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
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%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test5
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; Mask: [0,1,6,7]
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; CHECK: blendps $12
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; CHECK: ret
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; Verify that we fold shuffles according to rule:
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; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
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define <4 x float> @test6(<4 x float> %a) {
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%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
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%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test6
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; Mask: [0,1,2,3]
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; CHECK-NOT: pshufd
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; CHECK-NOT: shufps
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; CHECK-NOT: movlhps
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; CHECK: ret
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define <4 x float> @test7(<4 x float> %a) {
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%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
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%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test7
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; Mask: [0,1,0,1]
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; CHECK-NOT: pshufd
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; CHECK-NOT: shufps
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; CHECK: movlhps
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; CHECK-NEXT: ret
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define <4 x float> @test8(<4 x float> %a) {
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%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
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%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test8
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; Mask: [0,1,0,u]
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; CHECK-NOT: pshufd
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; CHECK-NOT: shufps
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; CHECK: movlhps
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; CHECK-NEXT: ret
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define <4 x float> @test9(<4 x float> %a) {
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%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
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%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test9
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; Mask: [2,3,2,3]
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; CHECK-NOT: movlhps
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; CHECK-NOT: palignr
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; CHECK: movhlps
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; CHECK-NEXT: ret
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define <4 x float> @test10(<4 x float> %a) {
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%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
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%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test10
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; Mask: [0,1,2,3]
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; CHECK-NOT: pshufd
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; CHECK-NOT: shufps
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; CHECK-NOT: movlhps
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; CHECK: ret
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