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https://github.com/c64scene-ar/llvm-6502.git
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Also handle ConstantAggregateZero when optimizing vpermilvar*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207582 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -724,11 +724,10 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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case Intrinsic::x86_avx_vpermilvar_pd_256: {
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case Intrinsic::x86_avx_vpermilvar_pd_256: {
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// Convert vpermil* to shufflevector if the mask is constant.
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// Convert vpermil* to shufflevector if the mask is constant.
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Value *V = II->getArgOperand(1);
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Value *V = II->getArgOperand(1);
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unsigned Size = cast<VectorType>(V->getType())->getNumElements();
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assert(Size == 8 || Size == 4 || Size == 2);
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uint32_t Indexes[8];
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if (auto C = dyn_cast<ConstantDataVector>(V)) {
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if (auto C = dyn_cast<ConstantDataVector>(V)) {
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unsigned Size = C->getNumElements();
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assert(Size == 8 || Size == 4 || Size == 2);
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uint32_t Indexes[8];
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// The intrinsics only read one or two bits, clear the rest.
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// The intrinsics only read one or two bits, clear the rest.
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for (unsigned I = 0; I < Size; ++I) {
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for (unsigned I = 0; I < Size; ++I) {
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uint32_t Index = C->getElementAsInteger(I) & 0x3;
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uint32_t Index = C->getElementAsInteger(I) & 0x3;
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@@ -737,23 +736,26 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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Index >>= 1;
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Index >>= 1;
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Indexes[I] = Index;
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Indexes[I] = Index;
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}
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}
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} else if (isa<ConstantAggregateZero>(V)) {
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// The _256 variants are a bit trickier since the mask bits always index
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for (unsigned I = 0; I < Size; ++I)
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// into the corresponding 128 half. In order to convert to a generic
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Indexes[I] = 0;
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// shuffle, we have to make that explicit.
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} else {
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if (II->getIntrinsicID() == Intrinsic::x86_avx_vpermilvar_ps_256 ||
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break;
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II->getIntrinsicID() == Intrinsic::x86_avx_vpermilvar_pd_256) {
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for (unsigned I = Size / 2; I < Size; ++I)
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Indexes[I] += Size / 2;
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}
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auto NewC =
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ConstantDataVector::get(C->getContext(), makeArrayRef(Indexes, Size));
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auto V1 = II->getArgOperand(0);
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auto V2 = UndefValue::get(V1->getType());
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auto Shuffle = Builder->CreateShuffleVector(V1, V2, NewC);
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return ReplaceInstUsesWith(CI, Shuffle);
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}
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}
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break;
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// The _256 variants are a bit trickier since the mask bits always index
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// into the corresponding 128 half. In order to convert to a generic
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// shuffle, we have to make that explicit.
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if (II->getIntrinsicID() == Intrinsic::x86_avx_vpermilvar_ps_256 ||
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II->getIntrinsicID() == Intrinsic::x86_avx_vpermilvar_pd_256) {
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for (unsigned I = Size / 2; I < Size; ++I)
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Indexes[I] += Size / 2;
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}
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auto NewC =
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ConstantDataVector::get(V->getContext(), makeArrayRef(Indexes, Size));
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auto V1 = II->getArgOperand(0);
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auto V2 = UndefValue::get(V1->getType());
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auto Shuffle = Builder->CreateShuffleVector(V1, V2, NewC);
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return ReplaceInstUsesWith(CI, Shuffle);
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}
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}
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case Intrinsic::ppc_altivec_vperm:
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case Intrinsic::ppc_altivec_vperm:
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@@ -339,6 +339,34 @@ define <4 x double> @test_vpermilvar_pd_256(<4 x double> %v) {
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ret <4 x double> %a
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ret <4 x double> %a
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}
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}
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define <4 x float> @test_vpermilvar_ps_zero(<4 x float> %v) {
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; CHECK-LABEL: @test_vpermilvar_ps_zero(
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; CHECK: shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> zeroinitializer
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%a = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %v, <4 x i32> zeroinitializer)
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ret <4 x float> %a
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}
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define <8 x float> @test_vpermilvar_ps_256_zero(<8 x float> %v) {
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; CHECK-LABEL: @test_vpermilvar_ps_256_zero(
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; CHECK: shufflevector <8 x float> %v, <8 x float> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4>
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%a = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %v, <8 x i32> zeroinitializer)
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ret <8 x float> %a
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}
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define <2 x double> @test_vpermilvar_pd_zero(<2 x double> %v) {
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; CHECK-LABEL: @test_vpermilvar_pd_zero(
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; CHECK: shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> zeroinitializer
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%a = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %v, <2 x i32> zeroinitializer)
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ret <2 x double> %a
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}
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define <4 x double> @test_vpermilvar_pd_256_zero(<4 x double> %v) {
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; CHECK-LABEL: @test_vpermilvar_pd_256_zero(
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; CHECK: shufflevector <4 x double> %v, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
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%a = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %v, <4 x i32> zeroinitializer)
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ret <4 x double> %a
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}
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define <2 x i64> @test_sse2_1() nounwind readnone uwtable {
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define <2 x i64> @test_sse2_1() nounwind readnone uwtable {
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%S = bitcast i32 1 to i32
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%S = bitcast i32 1 to i32
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%1 = zext i32 %S to i64
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%1 = zext i32 %S to i64
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