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https://github.com/c64scene-ar/llvm-6502.git
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Expand Op0Mask by one bit in preparation for the PadLock prefixes.
Define most shift masks incrementally to reduce the redundant hard-coding. Introduce new shift for the VEX flags to replace the magic constant 32 in various places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128822 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joerg Sonnenberger
parent
6c8afd728e
commit
229e4523f2
@ -91,21 +91,21 @@ class REX_W { bit hasREX_WPrefix = 1; }
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class LOCK { bit hasLockPrefix = 1; }
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class SegFS { bits<2> SegOvrBits = 1; }
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class SegGS { bits<2> SegOvrBits = 2; }
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class TB { bits<4> Prefix = 1; }
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class REP { bits<4> Prefix = 2; }
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class D8 { bits<4> Prefix = 3; }
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class D9 { bits<4> Prefix = 4; }
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class DA { bits<4> Prefix = 5; }
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class DB { bits<4> Prefix = 6; }
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class DC { bits<4> Prefix = 7; }
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class DD { bits<4> Prefix = 8; }
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class DE { bits<4> Prefix = 9; }
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class DF { bits<4> Prefix = 10; }
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class XD { bits<4> Prefix = 11; }
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class XS { bits<4> Prefix = 12; }
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class T8 { bits<4> Prefix = 13; }
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class TA { bits<4> Prefix = 14; }
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class TF { bits<4> Prefix = 15; }
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class TB { bits<5> Prefix = 1; }
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class REP { bits<5> Prefix = 2; }
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class D8 { bits<5> Prefix = 3; }
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class D9 { bits<5> Prefix = 4; }
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class DA { bits<5> Prefix = 5; }
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class DB { bits<5> Prefix = 6; }
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class DC { bits<5> Prefix = 7; }
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class DD { bits<5> Prefix = 8; }
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class DE { bits<5> Prefix = 9; }
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class DF { bits<5> Prefix = 10; }
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class XD { bits<5> Prefix = 11; }
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class XS { bits<5> Prefix = 12; }
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class T8 { bits<5> Prefix = 13; }
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class TA { bits<5> Prefix = 14; }
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class TF { bits<5> Prefix = 15; }
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class VEX { bit hasVEXPrefix = 1; }
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class VEX_W { bit hasVEX_WPrefix = 1; }
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class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
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@ -136,7 +136,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
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bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
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bits<4> Prefix = 0; // Which prefix byte does this inst have?
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bits<5> Prefix = 0; // Which prefix byte does this inst have?
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bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
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FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
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bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
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@ -154,20 +154,20 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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let TSFlags{5-0} = FormBits;
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let TSFlags{6} = hasOpSizePrefix;
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let TSFlags{7} = hasAdSizePrefix;
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let TSFlags{11-8} = Prefix;
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let TSFlags{12} = hasREX_WPrefix;
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let TSFlags{15-13} = ImmT.Value;
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let TSFlags{18-16} = FPForm.Value;
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let TSFlags{19} = hasLockPrefix;
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let TSFlags{21-20} = SegOvrBits;
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let TSFlags{23-22} = ExeDomain.Value;
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let TSFlags{31-24} = Opcode;
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let TSFlags{32} = hasVEXPrefix;
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let TSFlags{33} = hasVEX_WPrefix;
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let TSFlags{34} = hasVEX_4VPrefix;
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let TSFlags{35} = hasVEX_i8ImmReg;
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let TSFlags{36} = hasVEX_L;
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let TSFlags{37} = has3DNow0F0FOpcode;
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let TSFlags{12-8} = Prefix;
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let TSFlags{13} = hasREX_WPrefix;
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let TSFlags{16-14} = ImmT.Value;
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let TSFlags{19-17} = FPForm.Value;
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let TSFlags{20} = hasLockPrefix;
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let TSFlags{22-21} = SegOvrBits;
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let TSFlags{24-23} = ExeDomain.Value;
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let TSFlags{32-25} = Opcode;
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let TSFlags{33} = hasVEXPrefix;
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let TSFlags{34} = hasVEX_WPrefix;
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let TSFlags{35} = hasVEX_4VPrefix;
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let TSFlags{36} = hasVEX_i8ImmReg;
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let TSFlags{37} = hasVEX_L;
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let TSFlags{38} = has3DNow0F0FOpcode;
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}
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class PseudoI<dag oops, dag iops, list<dag> pattern>
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@ -347,7 +347,7 @@ namespace X86II {
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// set, there is no prefix byte for obtaining a multibyte opcode.
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//
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Op0Shift = 8,
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Op0Mask = 0xF << Op0Shift,
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Op0Mask = 0x1F << Op0Shift,
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// TB - TwoByte - Set if this instruction has a two byte opcode, which
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// starts with a 0x0F byte before the real opcode.
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@ -380,13 +380,13 @@ namespace X86II {
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// etc. We only cares about REX.W and REX.R bits and only the former is
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// statically determined.
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//
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REXShift = 12,
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REXShift = Op0Shift + 5,
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REX_W = 1 << REXShift,
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//===------------------------------------------------------------------===//
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// This three-bit field describes the size of an immediate operand. Zero is
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// unused so that we can tell if we forgot to set a value.
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ImmShift = 13,
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ImmShift = REXShift + 1,
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ImmMask = 7 << ImmShift,
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Imm8 = 1 << ImmShift,
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Imm8PCRel = 2 << ImmShift,
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@ -400,7 +400,7 @@ namespace X86II {
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// FP Instruction Classification... Zero is non-fp instruction.
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// FPTypeMask - Mask for all of the FP types...
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FPTypeShift = 16,
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FPTypeShift = ImmShift + 3,
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FPTypeMask = 7 << FPTypeShift,
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// NotFP - The default, set for instructions that do not use FP registers.
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@ -433,25 +433,26 @@ namespace X86II {
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SpecialFP = 7 << FPTypeShift,
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// Lock prefix
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LOCKShift = 19,
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LOCKShift = FPTypeShift + 3,
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LOCK = 1 << LOCKShift,
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// Segment override prefixes. Currently we just need ability to address
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// stuff in gs and fs segments.
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SegOvrShift = 20,
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SegOvrShift = LOCKShift + 1,
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SegOvrMask = 3 << SegOvrShift,
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FS = 1 << SegOvrShift,
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GS = 2 << SegOvrShift,
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// Execution domain for SSE instructions in bits 22, 23.
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// 0 in bits 22-23 means normal, non-SSE instruction.
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SSEDomainShift = 22,
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// Execution domain for SSE instructions in bits 23, 24.
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// 0 in bits 23-24 means normal, non-SSE instruction.
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SSEDomainShift = SegOvrShift + 2,
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OpcodeShift = 24,
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OpcodeShift = SSEDomainShift + 2,
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OpcodeMask = 0xFF << OpcodeShift,
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//===------------------------------------------------------------------===//
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/// VEX - The opcode prefix used by AVX instructions
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VEXShift = OpcodeShift + 8,
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VEX = 1U << 0,
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/// VEX_W - Has a opcode specific functionality, but is used in the same
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@ -549,7 +550,7 @@ namespace X86II {
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case X86II::MRMDestMem:
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return 0;
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case X86II::MRMSrcMem: {
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bool HasVEX_4V = (TSFlags >> 32) & X86II::VEX_4V;
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bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
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unsigned FirstMemOp = 1;
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if (HasVEX_4V)
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++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
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@ -382,7 +382,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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const TargetInstrDesc &Desc,
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raw_ostream &OS) const {
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bool HasVEX_4V = false;
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if ((TSFlags >> 32) & X86II::VEX_4V)
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
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HasVEX_4V = true;
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// VEX_R: opcode externsion equivalent to REX.R in
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@ -446,10 +446,10 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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if (TSFlags & X86II::OpSize)
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VEX_PP = 0x01;
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if ((TSFlags >> 32) & X86II::VEX_W)
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
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VEX_W = 1;
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if ((TSFlags >> 32) & X86II::VEX_L)
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
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VEX_L = 1;
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switch (TSFlags & X86II::Op0Mask) {
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@ -518,7 +518,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// If the last register should be encoded in the immediate field
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// do not use any bit from VEX prefix to this register, ignore it
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if ((TSFlags >> 32) & X86II::VEX_I8IMM)
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM)
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NumOps--;
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for (; CurOp != NumOps; ++CurOp) {
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@ -819,9 +819,9 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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// It uses the VEX.VVVV field?
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bool HasVEX_4V = false;
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if ((TSFlags >> 32) & X86II::VEX)
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX)
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HasVEXPrefix = true;
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if ((TSFlags >> 32) & X86II::VEX_4V)
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
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HasVEX_4V = true;
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@ -837,7 +837,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
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if ((TSFlags >> 32) & X86II::Has3DNow0F0FOpcode)
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if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
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BaseOpcode = 0x0F; // Weird 3DNow! encoding.
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unsigned SrcRegNum = 0;
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@ -994,7 +994,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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if (CurOp != NumOps) {
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// The last source register of a 4 operand instruction in AVX is encoded
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// in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
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if ((TSFlags >> 32) & X86II::VEX_I8IMM) {
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
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const MCOperand &MO = MI.getOperand(CurOp++);
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bool IsExtReg =
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X86InstrInfo::isX86_64ExtendedReg(MO.getReg());
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@ -1017,7 +1017,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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}
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}
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if ((TSFlags >> 32) & X86II::Has3DNow0F0FOpcode)
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if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
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EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
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