6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-29 15:17:14 +00:00
Code Issues Projects Releases Wiki Activity

Use enums instead of literals for X86 subregisters.

Browse Source 
The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104611 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2010-05-25 17:04:16 +00:00
parent f3c770a2cb
commit 22c0e97c56
2 changed files with 10 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/X86/X86InstrInfo.cpp
View File

@@ -744,17 +744,17 @@ X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
case X86::MOVZX32rr8: case X86::MOVZX32rr8:
case X86::MOVSX64rr8: case X86::MOVSX64rr8:
case X86::MOVZX64rr8: case X86::MOVZX64rr8:
SubIdx = 1; SubIdx = X86::sub_8bit;
break; break;
case X86::MOVSX32rr16: case X86::MOVSX32rr16:
case X86::MOVZX32rr16: case X86::MOVZX32rr16:
case X86::MOVSX64rr16: case X86::MOVSX64rr16:
case X86::MOVZX64rr16: case X86::MOVZX64rr16:
SubIdx = 3; SubIdx = X86::sub_16bit;
break; break;
case X86::MOVSX64rr32: case X86::MOVSX64rr32:
case X86::MOVZX64rr32: case X86::MOVZX64rr32:
SubIdx = 4; SubIdx = X86::sub_32bit;
break; break;
} }
return true; return true;

15
lib/Target/X86/X86RegisterInfo.cpp
View File

@@ -157,8 +157,8 @@ X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
unsigned SubIdx) const { unsigned SubIdx) const {
switch (SubIdx) { switch (SubIdx) {
default: return 0; default: return 0;
case 1: case X86::sub_8bit:
// 8-bit //case X86::sub_ss:
if (B == &X86::GR8RegClass) { if (B == &X86::GR8RegClass) {
if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8) if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
return A; return A;
@@ -194,8 +194,8 @@ X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
return A; return A;
} }
break; break;
case 2: case X86::sub_8bit_hi:
// 8-bit hi //case X86::sub_sd:
if (B == &X86::GR8_ABCD_HRegClass) { if (B == &X86::GR8_ABCD_HRegClass) {
if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass || if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
A == &X86::GR64_NOREXRegClass || A == &X86::GR64_NOREXRegClass ||
@@ -212,8 +212,8 @@ X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
return A; return A;
} }
break; break;
case 3: case X86::sub_16bit:
// 16-bit //case X86::sub_xmm:
if (B == &X86::GR16RegClass) { if (B == &X86::GR16RegClass) {
if (A->getSize() == 4 || A->getSize() == 8) if (A->getSize() == 4 || A->getSize() == 8)
return A; return A;
@@ -241,8 +241,7 @@ X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
return A; return A;
} }
break; break;
case 4: case X86::sub_32bit:
// 32-bit
if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) { if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
if (A->getSize() == 8) if (A->getSize() == 8)
return A; return A;