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Adding IV chain generation to LSR.
After collecting chains, check if any should be materialized. If so, hide the chained IV users from the LSR solver. LSR will only solve for the head of the chain. GenerateIVChains will then materialize the chained IV users by computing the IV relative to its previous value in the chain. In theory, chained IV users could be exposed to LSR's solver. This would be considerably complicated to implement and I'm not aware of a case where we need it. In practice it's more important to intelligently prune the search space of nontrivial loops before running the solver, otherwise the solver is often forced to prune the most optimal solutions. Hiding the chained users does this well, so that LSR is more likely to find the best IV for the chain as a whole. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147801 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
parent
6c7d0ae8dc
commit
22d20c218a
@ -91,6 +91,15 @@ static cl::opt<bool> EnablePhiElim(
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"enable-lsr-phielim", cl::Hidden, cl::init(true),
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cl::desc("Enable LSR phi elimination"));
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#ifndef NDEBUG
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// Stress test IV chain generation.
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static cl::opt<bool> StressIVChain(
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"stress-ivchain", cl::Hidden, cl::init(false),
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cl::desc("Stress test LSR IV chains"));
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#else
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static bool StressIVChain = false;
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#endif
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namespace {
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/// RegSortData - This class holds data which is used to order reuse candidates.
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@ -1415,6 +1424,9 @@ class LSRInstance {
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/// IVChainVec - IV users can form a chain of IV increments.
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SmallVector<IVChain, MaxChains> IVChainVec;
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/// IVIncSet - IV users that belong to profitable IVChains.
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SmallPtrSet<Use*, MaxChains> IVIncSet;
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void OptimizeShadowIV();
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bool FindIVUserForCond(ICmpInst *Cond, IVStrideUse *&CondUse);
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ICmpInst *OptimizeMax(ICmpInst *Cond, IVStrideUse* &CondUse);
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@ -1422,7 +1434,10 @@ class LSRInstance {
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void ChainInstruction(Instruction *UserInst, Instruction *IVOper,
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SmallVectorImpl<ChainUsers> &ChainUsersVec);
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void FinalizeChain(IVChain &Chain);
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void CollectChains();
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void GenerateIVChain(const IVChain &Chain, SCEVExpander &Rewriter,
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SmallVectorImpl<WeakVH> &DeadInsts);
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void CollectInterestingTypesAndFactors();
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void CollectFixupsAndInitialFormulae();
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@ -2189,6 +2204,48 @@ static bool isCompatibleIVType(Value *LVal, Value *RVal) {
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return (LType == RType) || (LType->isPointerTy() && RType->isPointerTy());
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}
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/// Return true if the chain increment is profitable to expand into a loop
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/// invariant value, which may require its own register. A profitable chain
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/// increment will be an offset relative to the same base. We allow such offsets
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/// to potentially be used as chain increment as long as it's not obviously
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/// expensive to expand using real instructions.
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static const SCEV *
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getProfitableChainIncrement(Value *NextIV, Value *PrevIV,
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const IVChain &Chain, Loop *L,
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ScalarEvolution &SE, const TargetLowering *TLI) {
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const SCEV *IncExpr = SE.getMinusSCEV(SE.getSCEV(NextIV), SE.getSCEV(PrevIV));
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if (!SE.isLoopInvariant(IncExpr, L))
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return 0;
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// We are not able to expand an increment unless it is loop invariant,
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// however, the following checks are purely for profitability.
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if (StressIVChain)
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return IncExpr;
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// Unimplemented
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return 0;
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}
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/// Return true if the number of registers needed for the chain is estimated to
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/// be less than the number required for the individual IV users. First prohibit
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/// any IV users that keep the IV live across increments (the Users set should
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/// be empty). Next count the number and type of increments in the chain.
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///
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/// Chaining IVs can lead to considerable code bloat if ISEL doesn't
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/// effectively use postinc addressing modes. Only consider it profitable it the
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/// increments can be computed in fewer registers when chained.
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///
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/// TODO: Consider IVInc free if it's already used in another chains.
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static bool
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isProfitableChain(IVChain &Chain, SmallPtrSet<Instruction*, 4> &Users,
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ScalarEvolution &SE, const TargetLowering *TLI) {
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if (StressIVChain)
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return true;
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// Unimplemented
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return false;
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}
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/// ChainInstruction - Add this IV user to an existing chain or make it the head
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/// of a new chain.
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void LSRInstance::ChainInstruction(Instruction *UserInst, Instruction *IVOper,
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@ -2211,9 +2268,9 @@ void LSRInstance::ChainInstruction(Instruction *UserInst, Instruction *IVOper,
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&& isa<PHINode>(IVChainVec[ChainIdx].back().UserInst))
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continue;
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const SCEV *IncExpr = SE.getMinusSCEV(SE.getSCEV(NextIV),
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SE.getSCEV(PrevIV));
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if (SE.isLoopInvariant(IncExpr, L)) {
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if (const SCEV *IncExpr =
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getProfitableChainIncrement(NextIV, PrevIV, IVChainVec[ChainIdx],
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L, SE, TLI)) {
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LastIncExpr = IncExpr;
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break;
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}
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@ -2223,7 +2280,7 @@ void LSRInstance::ChainInstruction(Instruction *UserInst, Instruction *IVOper,
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if (ChainIdx == NChains) {
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if (isa<PHINode>(UserInst))
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return;
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if (NChains >= MaxChains) {
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if (NChains >= MaxChains && !StressIVChain) {
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DEBUG(dbgs() << "IV Chain Limit\n");
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return;
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}
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@ -2349,13 +2406,173 @@ void LSRInstance::CollectChains() {
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if (IncV)
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ChainInstruction(PN, IncV, ChainUsersVec);
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}
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// Remove any unprofitable chains.
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unsigned ChainIdx = 0;
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for (unsigned UsersIdx = 0, NChains = IVChainVec.size();
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UsersIdx < NChains; ++UsersIdx) {
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if (!isProfitableChain(IVChainVec[UsersIdx],
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ChainUsersVec[UsersIdx].FarUsers, SE, TLI))
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continue;
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// Preserve the chain at UsesIdx.
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if (ChainIdx != UsersIdx)
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IVChainVec[ChainIdx] = IVChainVec[UsersIdx];
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FinalizeChain(IVChainVec[ChainIdx]);
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++ChainIdx;
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}
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IVChainVec.resize(ChainIdx);
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}
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void LSRInstance::FinalizeChain(IVChain &Chain) {
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assert(!Chain.empty() && "empty IV chains are not allowed");
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DEBUG(dbgs() << "Final Chain: " << *Chain[0].UserInst << "\n");
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for (IVChain::const_iterator I = llvm::next(Chain.begin()), E = Chain.end();
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I != E; ++I) {
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DEBUG(dbgs() << " Inc: " << *I->UserInst << "\n");
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User::op_iterator UseI =
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std::find(I->UserInst->op_begin(), I->UserInst->op_end(), I->IVOperand);
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assert(UseI != I->UserInst->op_end() && "cannot find IV operand");
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IVIncSet.insert(UseI);
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}
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}
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/// Return true if the IVInc can be folded into an addressing mode.
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static bool canFoldIVIncExpr(const SCEV *IncExpr, Instruction *UserInst,
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Value *Operand, const TargetLowering *TLI) {
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const SCEVConstant *IncConst = dyn_cast<SCEVConstant>(IncExpr);
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if (!IncConst || !isAddressUse(UserInst, Operand))
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return false;
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if (IncConst->getValue()->getValue().getMinSignedBits() > 64)
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return false;
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int64_t IncOffset = IncConst->getValue()->getSExtValue();
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if (!isAlwaysFoldable(IncOffset, /*BaseGV=*/0, /*HaseBaseReg=*/false,
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LSRUse::Address, getAccessType(UserInst), TLI))
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return false;
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return true;
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}
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/// GenerateIVChains - Generate an add or subtract for each IVInc in a chain to
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/// materialize the IV user's operand from the previous IV user's operand.
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void LSRInstance::GenerateIVChain(const IVChain &Chain, SCEVExpander &Rewriter,
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SmallVectorImpl<WeakVH> &DeadInsts) {
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// Find the new IVOperand for the head of the chain. It may have been replaced
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// by LSR.
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const IVInc &Head = Chain[0];
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User::op_iterator IVOpEnd = Head.UserInst->op_end();
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User::op_iterator IVOpIter = findIVOperand(Head.UserInst->op_begin(),
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IVOpEnd, L, SE);
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Value *IVSrc = 0;
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while (IVOpIter != IVOpEnd) {
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IVSrc = getWideOperand(*IVOpIter);
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// If this operand computes the expression that the chain needs, we may use
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// it. (Check this after setting IVSrc which is used below.)
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//
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// Note that if Head.IncExpr is wider than IVSrc, then this phi is too
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// narrow for the chain, so we can no longer use it. We do allow using a
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// wider phi, assuming the LSR checked for free truncation. In that case we
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// should already have a truncate on this operand such that
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// getSCEV(IVSrc) == IncExpr.
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if (SE.getSCEV(*IVOpIter) == Head.IncExpr
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|| SE.getSCEV(IVSrc) == Head.IncExpr) {
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break;
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}
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IVOpIter = findIVOperand(llvm::next(IVOpIter), IVOpEnd, L, SE);
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}
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if (IVOpIter == IVOpEnd) {
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// Gracefully give up on this chain.
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DEBUG(dbgs() << "Concealed chain head: " << *Head.UserInst << "\n");
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return;
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}
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DEBUG(dbgs() << "Generate chain at: " << *IVSrc << "\n");
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Type *IVTy = IVSrc->getType();
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Type *IntTy = SE.getEffectiveSCEVType(IVTy);
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const SCEV *LeftOverExpr = 0;
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for (IVChain::const_iterator IncI = llvm::next(Chain.begin()),
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IncE = Chain.end(); IncI != IncE; ++IncI) {
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Instruction *InsertPt = IncI->UserInst;
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if (isa<PHINode>(InsertPt))
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InsertPt = L->getLoopLatch()->getTerminator();
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// IVOper will replace the current IV User's operand. IVSrc is the IV
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// value currently held in a register.
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Value *IVOper = IVSrc;
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if (!IncI->IncExpr->isZero()) {
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// IncExpr was the result of subtraction of two narrow values, so must
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// be signed.
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const SCEV *IncExpr = SE.getNoopOrSignExtend(IncI->IncExpr, IntTy);
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LeftOverExpr = LeftOverExpr ?
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SE.getAddExpr(LeftOverExpr, IncExpr) : IncExpr;
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}
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if (LeftOverExpr && !LeftOverExpr->isZero()) {
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// Expand the IV increment.
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Rewriter.clearPostInc();
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Value *IncV = Rewriter.expandCodeFor(LeftOverExpr, IntTy, InsertPt);
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const SCEV *IVOperExpr = SE.getAddExpr(SE.getUnknown(IVSrc),
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SE.getUnknown(IncV));
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IVOper = Rewriter.expandCodeFor(IVOperExpr, IVTy, InsertPt);
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// If an IV increment can't be folded, use it as the next IV value.
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if (!canFoldIVIncExpr(LeftOverExpr, IncI->UserInst, IncI->IVOperand,
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TLI)) {
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assert(IVTy == IVOper->getType() && "inconsistent IV increment type");
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IVSrc = IVOper;
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LeftOverExpr = 0;
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}
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}
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Type *OperTy = IncI->IVOperand->getType();
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if (IVTy != OperTy) {
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assert(SE.getTypeSizeInBits(IVTy) >= SE.getTypeSizeInBits(OperTy) &&
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"cannot extend a chained IV");
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IRBuilder<> Builder(InsertPt);
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IVOper = Builder.CreateTruncOrBitCast(IVOper, OperTy, "lsr.chain");
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}
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IncI->UserInst->replaceUsesOfWith(IncI->IVOperand, IVOper);
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DeadInsts.push_back(IncI->IVOperand);
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}
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// If LSR created a new, wider phi, we may also replace its postinc. We only
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// do this if we also found a wide value for the head of the chain.
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if (isa<PHINode>(Chain.back().UserInst)) {
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for (BasicBlock::iterator I = L->getHeader()->begin();
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PHINode *Phi = dyn_cast<PHINode>(I); ++I) {
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if (!isCompatibleIVType(Phi, IVSrc))
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continue;
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Instruction *PostIncV = dyn_cast<Instruction>(
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Phi->getIncomingValueForBlock(L->getLoopLatch()));
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if (!PostIncV || (SE.getSCEV(PostIncV) != SE.getSCEV(IVSrc)))
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continue;
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Value *IVOper = IVSrc;
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Type *PostIncTy = PostIncV->getType();
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if (IVTy != PostIncTy) {
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assert(PostIncTy->isPointerTy() && "mixing int/ptr IV types");
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IRBuilder<> Builder(L->getLoopLatch()->getTerminator());
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Builder.SetCurrentDebugLocation(PostIncV->getDebugLoc());
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IVOper = Builder.CreatePointerCast(IVSrc, PostIncTy, "lsr.chain");
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}
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Phi->replaceUsesOfWith(PostIncV, IVOper);
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DeadInsts.push_back(PostIncV);
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}
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}
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}
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void LSRInstance::CollectFixupsAndInitialFormulae() {
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for (IVUsers::const_iterator UI = IU.begin(), E = IU.end(); UI != E; ++UI) {
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Instruction *UserInst = UI->getUser();
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// Skip IV users that are part of profitable IV Chains.
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User::op_iterator UseI = std::find(UserInst->op_begin(), UserInst->op_end(),
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UI->getOperandValToReplace());
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assert(UseI != UserInst->op_end() && "cannot find IV operand");
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if (IVIncSet.count(UseI))
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continue;
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// Record the uses.
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LSRFixup &LF = getNewFixup();
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LF.UserInst = UI->getUser();
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LF.UserInst = UserInst;
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LF.OperandValToReplace = UI->getOperandValToReplace();
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LF.PostIncLoops = UI->getPostIncLoops();
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@ -4073,6 +4290,11 @@ LSRInstance::ImplementSolution(const SmallVectorImpl<const Formula *> &Solution,
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Changed = true;
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}
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for (SmallVectorImpl<IVChain>::const_iterator ChainI = IVChainVec.begin(),
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ChainE = IVChainVec.end(); ChainI != ChainE; ++ChainI) {
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GenerateIVChain(*ChainI, Rewriter, DeadInsts);
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Changed = true;
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}
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// Clean up after ourselves. This must be done before deleting any
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// instructions.
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Rewriter.clear();
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@ -4123,6 +4345,7 @@ LSRInstance::LSRInstance(const TargetLowering *tli, Loop *l, Pass *P)
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CollectFixupsAndInitialFormulae();
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CollectLoopInvariantFixupsAndFormulae();
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assert(!Uses.empty() && "IVUsers reported at least one use");
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DEBUG(dbgs() << "LSR found " << Uses.size() << " uses:\n";
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print_uses(dbgs()));
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96
test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll
Normal file
96
test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll
Normal file
@ -0,0 +1,96 @@
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; REQUIRES: asserts
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; RUN: llc < %s -O3 -march=x86-64 -mcpu=core2 -stress-ivchain | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -O3 -march=x86 -mcpu=core2 -stress-ivchain | FileCheck %s -check-prefix=X32
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; @sharedidx is an unrolled variant of this loop:
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; for (unsigned long i = 0; i < len; i += s) {
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; c[i] = a[i] + b[i];
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; }
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; where 's' cannot be folded into the addressing mode.
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;
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; This is not quite profitable to chain. But with -stress-ivchain, we
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; can form three address chains in place of the shared induction
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; variable.
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; X64: sharedidx:
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; X64: %for.body.preheader
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; X64-NOT: leal ({{.*}},4)
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; X64: %for.body.1
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; X32: sharedidx:
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; X32: %for.body.2
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; X32: add
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; X32: add
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; X32: add
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; X32: add
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; X32: add
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; X32: %for.body.3
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define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp {
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entry:
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%cmp8 = icmp eq i32 %len, 0
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br i1 %cmp8, label %for.end, label %for.body
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for.body: ; preds = %entry, %for.body.3
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%i.09 = phi i32 [ %add5.3, %for.body.3 ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i8* %a, i32 %i.09
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%0 = load i8* %arrayidx, align 1
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%conv6 = zext i8 %0 to i32
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%arrayidx1 = getelementptr inbounds i8* %b, i32 %i.09
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%1 = load i8* %arrayidx1, align 1
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%conv27 = zext i8 %1 to i32
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%add = add nsw i32 %conv27, %conv6
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%conv3 = trunc i32 %add to i8
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%arrayidx4 = getelementptr inbounds i8* %c, i32 %i.09
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store i8 %conv3, i8* %arrayidx4, align 1
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%add5 = add i32 %i.09, %s
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%cmp = icmp ult i32 %add5, %len
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br i1 %cmp, label %for.body.1, label %for.end
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for.end: ; preds = %for.body, %for.body.1, %for.body.2, %for.body.3, %entry
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ret void
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for.body.1: ; preds = %for.body
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%arrayidx.1 = getelementptr inbounds i8* %a, i32 %add5
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%2 = load i8* %arrayidx.1, align 1
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%conv6.1 = zext i8 %2 to i32
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%arrayidx1.1 = getelementptr inbounds i8* %b, i32 %add5
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%3 = load i8* %arrayidx1.1, align 1
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%conv27.1 = zext i8 %3 to i32
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%add.1 = add nsw i32 %conv27.1, %conv6.1
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%conv3.1 = trunc i32 %add.1 to i8
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%arrayidx4.1 = getelementptr inbounds i8* %c, i32 %add5
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store i8 %conv3.1, i8* %arrayidx4.1, align 1
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%add5.1 = add i32 %add5, %s
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%cmp.1 = icmp ult i32 %add5.1, %len
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br i1 %cmp.1, label %for.body.2, label %for.end
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for.body.2: ; preds = %for.body.1
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%arrayidx.2 = getelementptr inbounds i8* %a, i32 %add5.1
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%4 = load i8* %arrayidx.2, align 1
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%conv6.2 = zext i8 %4 to i32
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%arrayidx1.2 = getelementptr inbounds i8* %b, i32 %add5.1
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%5 = load i8* %arrayidx1.2, align 1
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%conv27.2 = zext i8 %5 to i32
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%add.2 = add nsw i32 %conv27.2, %conv6.2
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%conv3.2 = trunc i32 %add.2 to i8
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%arrayidx4.2 = getelementptr inbounds i8* %c, i32 %add5.1
|
||||
store i8 %conv3.2, i8* %arrayidx4.2, align 1
|
||||
%add5.2 = add i32 %add5.1, %s
|
||||
%cmp.2 = icmp ult i32 %add5.2, %len
|
||||
br i1 %cmp.2, label %for.body.3, label %for.end
|
||||
|
||||
for.body.3: ; preds = %for.body.2
|
||||
%arrayidx.3 = getelementptr inbounds i8* %a, i32 %add5.2
|
||||
%6 = load i8* %arrayidx.3, align 1
|
||||
%conv6.3 = zext i8 %6 to i32
|
||||
%arrayidx1.3 = getelementptr inbounds i8* %b, i32 %add5.2
|
||||
%7 = load i8* %arrayidx1.3, align 1
|
||||
%conv27.3 = zext i8 %7 to i32
|
||||
%add.3 = add nsw i32 %conv27.3, %conv6.3
|
||||
%conv3.3 = trunc i32 %add.3 to i8
|
||||
%arrayidx4.3 = getelementptr inbounds i8* %c, i32 %add5.2
|
||||
store i8 %conv3.3, i8* %arrayidx4.3, align 1
|
||||
%add5.3 = add i32 %add5.2, %s
|
||||
%cmp.3 = icmp ult i32 %add5.3, %len
|
||||
br i1 %cmp.3, label %for.body, label %for.end
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user