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Add sanity checking for invalid register encodings for signed/unsigned extend instructions.

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Add some test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129098 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-07 19:28:58 +00:00
parent 8dbda0b51b
commit 22dc4d9f59
3 changed files with 22 additions and 0 deletions
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5
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -1589,6 +1589,11 @@ static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
static bool DisassembleExtFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
// A8.6.220 SXTAB
// if d == 15 || m == 15 then UNPREDICTABLE;
if (decodeRd(insn) == 15 || decodeRm(insn) == 15)
return false;
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
unsigned &OpIdx = NumOpsAdded;

6
test/MC/Disassembler/ARM/arm-tests.txt
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@ -248,3 +248,9 @@
# CHECK: lsl r3, r2, r1
0x12 0x31 0xa0 0xe1
# CHECK: sxtab r9, r8, r5
0x75 0x90 0xa8 0xe6
# CHECK: sxtb r9, r5, ror #8
0x75 0x94 0xaf 0xe6

11
test/MC/Disassembler/ARM/invalid-SXTB-arm.txt Normal file
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@ -0,0 +1,11 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1|
# -------------------------------------------------------------------------------------------------
#
# A8.6.223 SXTB
# if d == 15 || m == 15 then UNPREDICTABLE;
0x75 0xf4 0xaf 0xe6