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According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1

Browse Source 
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-04-19 21:19:52 +00:00
parent e9afbfe664
commit 22e401f5d4
2 changed files with 16 additions and 8 deletions
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21
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -3209,6 +3209,15 @@ bool ARMBasicMCBuilder::BuildIt(MCInst &MI, uint32_t insn) {
return TryPredicateAndSBitModifier(MI, Opcode, insn, NumOps - NumOpsAdded); return TryPredicateAndSBitModifier(MI, Opcode, insn, NumOps - NumOpsAdded);
} }
// A8.3 Conditional execution
// A8.3.1 Pseudocode details of conditional execution
// Condition bits '111x' indicate the instruction is always executed.
static uint32_t CondCode(uint32_t CondField) {
if (CondField == 0xF)
return ARMCC::AL;
return CondField;
}
bool ARMBasicMCBuilder::TryPredicateAndSBitModifier(MCInst& MI, unsigned Opcode, bool ARMBasicMCBuilder::TryPredicateAndSBitModifier(MCInst& MI, unsigned Opcode,
uint32_t insn, unsigned short NumOpsRemaining) { uint32_t insn, unsigned short NumOpsRemaining) {
@ -3236,18 +3245,14 @@ bool ARMBasicMCBuilder::TryPredicateAndSBitModifier(MCInst& MI, unsigned Opcode,
// //
// A8.6.16 B // A8.6.16 B
if (Name == "t2Bcc") if (Name == "t2Bcc")
MI.addOperand(MCOperand::CreateImm(slice(insn, 25, 22))); MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 25, 22))));
else if (Name == "tBcc") else if (Name == "tBcc")
MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 8))); MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 11, 8))));
else else
MI.addOperand(MCOperand::CreateImm(ARMCC::AL)); MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
} else { } else {
// ARM Instructions. Check condition field. // ARM instructions get their condition field from Inst{31-28}.
int64_t CondVal = getCondField(insn); MI.addOperand(MCOperand::CreateImm(CondCode(getCondField(insn))));
if (CondVal == 0xF)
MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
else
MI.addOperand(MCOperand::CreateImm(CondVal));
} }
} }
MI.addOperand(MCOperand::CreateReg(ARM::CPSR)); MI.addOperand(MCOperand::CreateReg(ARM::CPSR));

3
test/MC/Disassembler/thumb-tests.txt
View File

@ -9,6 +9,9 @@
# CHECK: b #34 # CHECK: b #34
0x0f 0xe0 0x0f 0xe0
# CHECK: b.w #-12
0xff 0xf7 0xf8 0xaf
# CHECK: bfi r2, r10, #0, #1 # CHECK: bfi r2, r10, #0, #1
0x6a 0xf3 0x00 0x02 0x6a 0xf3 0x00 0x02