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SelectNodeTo() may return a SDOperand that is different from the input.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29726 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2006-08-16 07:30:09 +00:00
parent 4b790573f7
commit 23329f5e03
5 changed files with 37 additions and 57 deletions
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29
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
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@@ -197,10 +197,9 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
case ISD::FrameIndex: { case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex(); int FI = cast<FrameIndexSDNode>(N)->getIndex();
Result = CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64, return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i32), CurDAG->getTargetFrameIndex(FI, MVT::i32),
getI64Imm(0)); getI64Imm(0)).Val;
return NULL;
} }
case AlphaISD::GlobalBaseReg: case AlphaISD::GlobalBaseReg:
Result = getGlobalBaseReg(); Result = getGlobalBaseReg();
@@ -228,8 +227,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
Chain, Chain.getValue(1)); Chain, Chain.getValue(1));
Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
SDOperand(CNode, 1)); SDOperand(CNode, 1));
Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain); return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain).Val;
return NULL;
} }
case ISD::READCYCLECOUNTER: { case ISD::READCYCLECOUNTER: {
@@ -266,24 +264,21 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64); SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
getGlobalBaseReg()); getGlobalBaseReg());
Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode()); CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode()).Val;
return NULL;
} }
case ISD::TargetConstantFP: { case ISD::TargetConstantFP: {
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N); ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
bool isDouble = N->getValueType(0) == MVT::f64; bool isDouble = N->getValueType(0) == MVT::f64;
MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32; MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
if (CN->isExactlyValue(+0.0)) { if (CN->isExactlyValue(+0.0)) {
Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS, return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
T, CurDAG->getRegister(Alpha::F31, T), T, CurDAG->getRegister(Alpha::F31, T),
CurDAG->getRegister(Alpha::F31, T)); CurDAG->getRegister(Alpha::F31, T)).Val;
return NULL;
} else if ( CN->isExactlyValue(-0.0)) { } else if ( CN->isExactlyValue(-0.0)) {
Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS, return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
T, CurDAG->getRegister(Alpha::F31, T), T, CurDAG->getRegister(Alpha::F31, T),
CurDAG->getRegister(Alpha::F31, T)); CurDAG->getRegister(Alpha::F31, T)).Val;
return NULL;
} else { } else {
abort(); abort();
} }

51
lib/Target/IA64/IA64ISelDAGToDAG.cpp
View File

@@ -398,25 +398,21 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so.. SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0)) { if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0)) {
Result = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64); return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64).Val;
} else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0)) { } else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0)) {
Result = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64); return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64).Val;
} else } else
assert(0 && "Unexpected FP constant!"); assert(0 && "Unexpected FP constant!");
return Result.Val;
} }
case ISD::FrameIndex: { // TODO: reduce creepyness case ISD::FrameIndex: { // TODO: reduce creepyness
int FI = cast<FrameIndexSDNode>(N)->getIndex(); int FI = cast<FrameIndexSDNode>(N)->getIndex();
if (N->hasOneUse()) { if (N->hasOneUse())
Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64, return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i64)); CurDAG->getTargetFrameIndex(FI, MVT::i64)).Val;
return NULL; else
} else { return SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
Result = SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64, CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0).Val;
CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0);
return Result.Val;
}
} }
case ISD::ConstantPool: { // TODO: nuke the constant pool case ISD::ConstantPool: { // TODO: nuke the constant pool
@@ -467,11 +463,10 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
case MVT::i1: { // this is a bool case MVT::i1: { // this is a bool
Opc = IA64::LD1; // first we load a byte, then compare for != 0 Opc = IA64::LD1; // first we load a byte, then compare for != 0
if(N->getValueType(0) == MVT::i1) { // XXX: early exit! if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
Result = CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0), SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
CurDAG->getRegister(IA64::r0, MVT::i64), CurDAG->getRegister(IA64::r0, MVT::i64),
Chain).getValue(Op.ResNo); Chain).getValue(Op.ResNo).Val;
return NULL;
} }
/* otherwise, we want to load a bool into something bigger: LD1 /* otherwise, we want to load a bool into something bigger: LD1
will do that for us, so we just fall through */ will do that for us, so we just fall through */
@@ -486,9 +481,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
} }
// TODO: comment this // TODO: comment this
Result = CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other, return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
Address, Chain).getValue(Op.ResNo); Address, Chain).getValue(Op.ResNo).Val;
return NULL;
} }
case ISD::TRUNCSTORE: case ISD::TRUNCSTORE:
@@ -512,8 +506,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial, Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
CurDAG->getConstant(1, MVT::i64), CurDAG->getConstant(1, MVT::i64),
Tmp), 0); Tmp), 0);
Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain); return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain).Val;
return NULL;
} }
case MVT::i64: Opc = IA64::ST8; break; case MVT::i64: Opc = IA64::ST8; break;
case MVT::f64: Opc = IA64::STF8; break; case MVT::f64: Opc = IA64::STF8; break;
@@ -531,8 +524,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
SDOperand N1, N2; SDOperand N1, N2;
AddToQueue(N1, N->getOperand(1)); AddToQueue(N1, N->getOperand(1));
AddToQueue(N2, N->getOperand(2)); AddToQueue(N2, N->getOperand(2));
Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain); return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain).Val;
return NULL;
} }
case ISD::BRCOND: { case ISD::BRCOND: {
@@ -542,9 +534,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
MachineBasicBlock *Dest = MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock(); cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
//FIXME - we do NOT need long branches all the time //FIXME - we do NOT need long branches all the time
Result = CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC, return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
CurDAG->getBasicBlock(Dest), Chain); CurDAG->getBasicBlock(Dest), Chain).Val;
return NULL;
} }
case ISD::CALLSEQ_START: case ISD::CALLSEQ_START:
@@ -554,17 +545,15 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP; IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
SDOperand N0; SDOperand N0;
AddToQueue(N0, N->getOperand(0)); AddToQueue(N0, N->getOperand(0));
Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0); return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0).Val;
return NULL;
} }
case ISD::BR: case ISD::BR:
// FIXME: we don't need long branches all the time! // FIXME: we don't need long branches all the time!
SDOperand N0; SDOperand N0;
AddToQueue(N0, N->getOperand(0)); AddToQueue(N0, N->getOperand(0));
Result = CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
N->getOperand(1), N0); N->getOperand(1), N0).Val;
return NULL;
} }
return SelectCode(Result, Op); return SelectCode(Result, Op);

6
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@@ -1093,8 +1093,8 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
// FIXME: Handle div by immediate. // FIXME: Handle div by immediate.
unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
Result = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
return NULL; TopPart).Val;
} }
case ISD::MULHU: case ISD::MULHU:
case ISD::MULHS: { case ISD::MULHS: {
@@ -1106,7 +1106,7 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
MulLHS, MulRHS); MulLHS, MulRHS);
// The high part is in the Y register. // The high part is in the Y register.
Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)).Val;
return NULL; return NULL;
} }
} }

3
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@@ -703,8 +703,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
if (C.Val) { if (C.Val) {
if (N.Val->hasOneUse()) { if (N.Val->hasOneUse()) {
Result = CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C); return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C).Val;
return NULL;
} else { } else {
SDNode *ResNode = CurDAG->getTargetNode(X86::MOV32ri, MVT::i32, C); SDNode *ResNode = CurDAG->getTargetNode(X86::MOV32ri, MVT::i32, C);
Result = SDOperand(ResNode, 0); Result = SDOperand(ResNode, 0);

5
utils/TableGen/DAGISelEmitter.cpp
View File

@@ -2794,8 +2794,6 @@ public:
if (NodeHasInFlag || HasImpInputs) if (NodeHasInFlag || HasImpInputs)
Code += ", InFlag"; Code += ", InFlag";
emitCode(Code + ");"); emitCode(Code + ");");
if (isRoot)
emitCode(" return NULL;");
emitCode("} else {"); emitCode("} else {");
emitDecl("ResNode", 1); emitDecl("ResNode", 1);
Code = " ResNode = CurDAG->getTargetNode(Opc" + utostr(OpcNo); Code = " ResNode = CurDAG->getTargetNode(Opc" + utostr(OpcNo);
@@ -2812,9 +2810,8 @@ public:
Code += ", InFlag"; Code += ", InFlag";
emitCode(Code + ");"); emitCode(Code + ");");
emitCode(" Result = SDOperand(ResNode, 0);"); emitCode(" Result = SDOperand(ResNode, 0);");
if (isRoot)
emitCode(" return Result.Val;");
emitCode("}"); emitCode("}");
emitCode("return Result.Val;");
} }
return std::make_pair(1, ResNo); return std::make_pair(1, ResNo);