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Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97159 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-02-25 18:46:43 +00:00
parent d74acb0c78
commit 2333655ed0
1 changed files with 50 additions and 0 deletions
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50
lib/Target/ARM/ARMInstrThumb2.td
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@ -1984,3 +1984,53 @@ def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
[(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
imm:$cp))]>,
Requires<[IsThumb2]>;
//===----------------------------------------------------------------------===//
// Move between special register and ARM core register -- for disassembly only
//
// Rd = Instr{11-8}
def t2MRS : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
let Inst{26} = 0;
let Inst{25-21} = 0b11111;
let Inst{20} = 0; // The R bit.
let Inst{15-14} = 0b10;
let Inst{12} = 0;
}
// Rd = Instr{11-8}
def t2MRSsys : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
let Inst{26} = 0;
let Inst{25-21} = 0b11111;
let Inst{20} = 1; // The R bit.
let Inst{15-14} = 0b10;
let Inst{12} = 0;
}
// FIXME: mask is ignored for the time being.
// Rn = Inst{19-16}
def t2MSR : T2I<(outs), (ins GPR:$src), NoItinerary, "msr", "\tcpsr, $src",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
let Inst{26} = 0;
let Inst{25-21} = 0b11100;
let Inst{20} = 0; // The R bit.
let Inst{15-14} = 0b10;
let Inst{12} = 0;
}
// FIXME: mask is ignored for the time being.
// Rn = Inst{19-16}
def t2MSRsys : T2I<(outs), (ins GPR:$src), NoItinerary, "msr", "\tspsr, $src",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
let Inst{26} = 0;
let Inst{25-21} = 0b11100;
let Inst{20} = 1; // The R bit.
let Inst{15-14} = 0b10;
let Inst{12} = 0;
}