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64-bit fp loads can come straight out of the constant pool, not as

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bad as I'd thought.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113561 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-09-09 23:50:00 +00:00
parent 70c2fc0823
commit 238bb16251
1 changed files with 18 additions and 10 deletions
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28
lib/Target/ARM/ARMFastISel.cpp
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@ -373,16 +373,24 @@ unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
.addFPImm(CFP));
return DestReg;
}
// No 64-bit at the moment.
if (is64bit) return 0;
// Load this from the constant pool.
unsigned DestReg = ARMMaterializeInt(cast<Constant>(CFP));
// If we have a floating point constant we expect it in a floating point
// register.
return ARMMoveToFPReg(VT, DestReg);
// Require VFP2 for this.
if (!Subtarget->hasVFP2()) return false;
// MachineConstantPool wants an explicit alignment.
unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
if (Align == 0) {
// TODO: Figure out if this is correct.
Align = TD.getTypeAllocSize(CFP->getType());
}
unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
.addReg(DestReg).addConstantPoolIndex(Idx)
.addReg(0));
return DestReg;
}
unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) {