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Header files for the target architecture description and for instruction
selection, and instances of these for the SPARC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve
421
include/llvm/CodeGen/Sparc.h
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421
include/llvm/CodeGen/Sparc.h
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// $Id$ -*-c++-*-
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//***************************************************************************
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// File:
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// Sparc.cpp
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//
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// Purpose:
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//
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// History:
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// 7/15/01 - Vikram Adve - Created
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//**************************************************************************/
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#ifndef LLVM_CODEGEN_SPARC_H
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#define LLVM_CODEGEN_SPARC_H
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//************************** System Include Files **************************/
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//*************************** User Include Files ***************************/
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#include "llvm/Codegen/TargetMachine.h"
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#include "llvm/Codegen/MachineInstr.h"
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//************************* Opaque Declarations ****************************/
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//************************ Exported Constants ******************************/
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// OpCodeMask definitions for the Sparc V9
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//
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const OpCodeMask Immed = 0x00002000; // immed or reg operand?
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const OpCodeMask Annul = 0x20000000; // annul delay instr?
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const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
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//************************ Exported Data Types *****************************/
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//---------------------------------------------------------------------------
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// class UltraSparcMachine
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//
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// Purpose:
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// Machine description.
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//
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//---------------------------------------------------------------------------
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class UltraSparc: public TargetMachine {
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public:
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/*ctor*/ UltraSparc ();
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/*dtor*/ virtual ~UltraSparc () {}
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};
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//---------------------------------------------------------------------------
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// enum SparcMachineOpCode.
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// const MachineInstrInfo SparcMachineInstrInfo[].
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//
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// Purpose:
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// Description of UltraSparc machine instructions.
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//
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//---------------------------------------------------------------------------
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enum SparcMachineOpCode {
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NOP,
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// Synthetic SPARC assembly opcodes for setting a register to a constant
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SETSW,
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SETUW,
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// Add or add with carry.
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// Immed bit specifies if second operand is immediate(1) or register(0)
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ADD,
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ADDcc,
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ADDC,
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ADDCcc,
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// Subtract or subtract with carry.
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// Immed bit specifies if second operand is immediate(1) or register(0)
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SUB,
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SUBcc,
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SUBC,
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SUBCcc,
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// Integer multiply, signed divide, unsigned divide.
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// Note that the deprecated 32-bit multiply and multiply-step are not used.
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MULX,
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SDIVX,
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UDIVX,
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// Floating point add, subtract, compare
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FADDS,
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FADDD,
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FADDQ,
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FSUBS,
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FSUBD,
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FSUBQ,
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FCMPS,
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FCMPD,
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FCMPQ,
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// NOTE: FCMPE{S,D,Q}: FP Compare With Exception are currently unused!
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// Floating point multiply or divide.
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FMULS,
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FMULD,
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FMULQ,
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FSMULD,
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FDMULQ,
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FDIVS,
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FDIVD,
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FDIVQ,
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// Logical operations
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AND,
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ANDcc,
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ANDN,
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ANDNcc,
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OR,
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ORcc,
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ORN,
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ORNcc,
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XOR,
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XORcc,
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XNOR,
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XNORcc,
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// Shift operations
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SLL,
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SRL,
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SRA,
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SLLX,
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SRLX,
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SRAX,
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// Convert from floating point to floating point formats
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FSTOD,
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FSTOQ,
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FDTOS,
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FDTOQ,
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FQTOS,
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FQTOD,
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// Convert from floating point to integer formats
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FSTOX,
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FDTOX,
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FQTOX,
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FSTOI,
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FDTOI,
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FQTOI,
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// Convert from integer to floating point formats
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FXTOS,
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FXTOD,
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FXTOQ,
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FITOS,
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FITOD,
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FITOQ,
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// Branch on integer comparison with zero.
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// Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
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// PredictTaken bit hints if branch should be predicted taken(1) or not(0).
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BRZ,
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BRLEZ,
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BRLZ,
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BRNZ,
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BRGZ,
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BRGEZ,
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// Branch on integer condition code.
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// Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
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// PredictTaken bit hints if branch should be predicted taken(1) or not(0).
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BA,
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BN,
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BNE,
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BE,
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BG,
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BLE,
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BGE,
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BL,
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BGU,
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BLEU,
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BCC,
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BCS,
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BPOS,
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BNEG,
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BVC,
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BVS,
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// Branch on floating point condition code.
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// Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
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// PredictTaken bit hints if branch should be predicted taken(1) or not(0).
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FBA,
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FBN,
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FBU,
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FBG,
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FBUG,
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FBL,
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FBUL,
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FBLG,
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FBNE,
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FBE,
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FBUE,
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FBGE,
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FBUGE,
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FBLE,
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FBULE,
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FBO,
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// Load integer instructions
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LDSB,
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LDSH,
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LDSW,
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LDUB,
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LDUH,
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LDUW,
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LDX,
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// Load floating-point instructions
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LD,
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LDD, // use of this for integers is deprecated for Sparc V9
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LDQ,
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// Store integer instructions
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STB,
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STH,
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STW,
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STX,
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// Store floating-point instructions
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ST,
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STD,
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// Call, Return, and "Jump and link"
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// Immed bit specifies if second operand is immediate(1) or register(0)
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CALL,
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JMPL,
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RETURN,
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// End-of-array marker
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INVALID_OPCODE
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};
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const MachineInstrInfo SparcMachineInstrInfo[] = {
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{ "NOP", 0, -1, 0, false },
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// Synthetic SPARC assembly opcodes for setting a register to a constant
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{ "SETSW", 2, 1, 0, true }, // max immediate constant is ignored
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{ "SETUW", 2, 1, 0, false }, // max immediate constant is ignored
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// Add or add with carry.
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{ "ADD", 3, 2, (1 << 12) - 1, true },
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{ "ADDcc", 3, 2, (1 << 12) - 1, true },
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{ "ADDC", 3, 2, (1 << 12) - 1, true },
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{ "ADDCcc", 3, 2, (1 << 12) - 1, true },
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// Sub tract or subtract with carry.
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{ "SUB", 3, 2, (1 << 12) - 1, true },
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{ "SUBcc", 3, 2, (1 << 12) - 1, true },
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{ "SUBC", 3, 2, (1 << 12) - 1, true },
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{ "SUBCcc", 3, 2, (1 << 12) - 1, true },
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// Integer multiply, signed divide, unsigned divide.
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// Note that the deprecated 32-bit multiply and multiply-step are not used.
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{ "MULX", 3, 2, (1 << 12) - 1, true },
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{ "SDIVX", 3, 2, (1 << 12) - 1, true },
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{ "UDIVX", 3, 2, (1 << 12) - 1, true },
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// Floating point add, subtract, compare
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{ "FADDS", 3, 2, 0, false },
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{ "FADDD", 3, 2, 0, false },
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{ "FADDQ", 3, 2, 0, false },
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{ "FSUBS", 3, 2, 0, false },
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{ "FSUBD", 3, 2, 0, false },
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{ "FSUBQ", 3, 2, 0, false },
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{ "FCMPS", 3, 2, 0, false },
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{ "FCMPD", 3, 2, 0, false },
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{ "FCMPQ", 3, 2, 0, false },
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// NOTE: FCMPE{S,D,Q}: FP Compare With Exception are currently unused!
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// Floating point multiply or divide.
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{ "FMULS", 3, 2, 0, false },
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{ "FMULD", 3, 2, 0, false },
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{ "FMULQ", 3, 2, 0, false },
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{ "FSMULD", 3, 2, 0, false },
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{ "FDMULQ", 3, 2, 0, false },
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{ "FDIVS", 3, 2, 0, false },
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{ "FDIVD", 3, 2, 0, false },
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{ "FDIVQ", 3, 2, 0, false },
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// Logical operations
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{ "AND", 3, 2, (1 << 12) - 1, true },
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{ "ANDcc", 3, 2, (1 << 12) - 1, true },
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{ "ANDN", 3, 2, (1 << 12) - 1, true },
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{ "ANDNcc", 3, 2, (1 << 12) - 1, true },
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{ "OR", 3, 2, (1 << 12) - 1, true },
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{ "ORcc", 3, 2, (1 << 12) - 1, true },
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{ "ORN", 3, 2, (1 << 12) - 1, true },
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{ "ORNcc", 3, 2, (1 << 12) - 1, true },
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{ "XOR", 3, 2, (1 << 12) - 1, true },
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{ "XORcc", 3, 2, (1 << 12) - 1, true },
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{ "XNOR", 3, 2, (1 << 12) - 1, true },
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{ "XNORcc", 3, 2, (1 << 12) - 1, true },
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// Shift operations
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{ "SLL", 3, 2, (1 << 5) - 1, true },
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{ "SRL", 3, 2, (1 << 5) - 1, true },
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{ "SRA", 3, 2, (1 << 5) - 1, true },
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{ "SLLX", 3, 2, (1 << 6) - 1, true },
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{ "SRLX", 3, 2, (1 << 6) - 1, true },
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{ "SRAX", 3, 2, (1 << 6) - 1, true },
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// Convert from floating point to floating point formats
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{ "FSTOD", 2, 1, 0, false },
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{ "FSTOQ", 2, 1, 0, false },
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{ "FDTOS", 2, 1, 0, false },
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{ "FDTOQ", 2, 1, 0, false },
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{ "FQTOS", 2, 1, 0, false },
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{ "FQTOD", 2, 1, 0, false },
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// Convert from floating point to integer formats
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{ "FSTOX", 2, 1, 0, false },
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{ "FDTOX", 2, 1, 0, false },
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{ "FQTOX", 2, 1, 0, false },
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{ "FSTOI", 2, 1, 0, false },
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{ "FDTOI", 2, 1, 0, false },
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{ "FQTOI", 2, 1, 0, false },
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// Convert from integer to floating point formats
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{ "FXTOS", 2, 1, 0, false },
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{ "FXTOD", 2, 1, 0, false },
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{ "FXTOQ", 2, 1, 0, false },
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{ "FITOS", 2, 1, 0, false },
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{ "FITOD", 2, 1, 0, false },
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{ "FITOQ", 2, 1, 0, false },
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// Branch on integer comparison with zero.
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{ "BRZ", 2, -1, (1 << 15) - 1, true },
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{ "BRLEZ", 2, -1, (1 << 15) - 1, true },
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{ "BRLZ", 2, -1, (1 << 15) - 1, true },
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{ "BRNZ", 2, -1, (1 << 15) - 1, true },
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{ "BRGZ", 2, -1, (1 << 15) - 1, true },
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{ "BRGEZ", 2, -1, (1 << 15) - 1, true },
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// Branch on condition code.
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{ "BA", 1, -1, (1 << 21) - 1, true },
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{ "BN", 1, -1, (1 << 21) - 1, true },
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{ "BNE", 1, -1, (1 << 21) - 1, true },
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{ "BE", 1, -1, (1 << 21) - 1, true },
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{ "BG", 1, -1, (1 << 21) - 1, true },
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{ "BLE", 1, -1, (1 << 21) - 1, true },
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{ "BGE", 1, -1, (1 << 21) - 1, true },
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{ "BL", 1, -1, (1 << 21) - 1, true },
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{ "BGU", 1, -1, (1 << 21) - 1, true },
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{ "BLEU", 1, -1, (1 << 21) - 1, true },
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{ "BCC", 1, -1, (1 << 21) - 1, true },
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{ "BCS", 1, -1, (1 << 21) - 1, true },
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{ "BPOS", 1, -1, (1 << 21) - 1, true },
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{ "BNEG", 1, -1, (1 << 21) - 1, true },
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{ "BVC", 1, -1, (1 << 21) - 1, true },
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{ "BVS", 1, -1, (1 << 21) - 1, true },
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// Branch on floating point condition code.
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// Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
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// PredictTaken bit hints if branch should be predicted taken(1) or not(0).
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// The first argument is the FCCn register (0 <= n <= 3).
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{ "FBA", 2, -1, (1 << 18) - 1, true },
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{ "FBN", 2, -1, (1 << 18) - 1, true },
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{ "FBU", 2, -1, (1 << 18) - 1, true },
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{ "FBG", 2, -1, (1 << 18) - 1, true },
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{ "FBUG", 2, -1, (1 << 18) - 1, true },
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{ "FBL", 2, -1, (1 << 18) - 1, true },
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{ "FBUL", 2, -1, (1 << 18) - 1, true },
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{ "FBLG", 2, -1, (1 << 18) - 1, true },
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{ "FBNE", 2, -1, (1 << 18) - 1, true },
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{ "FBE", 2, -1, (1 << 18) - 1, true },
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{ "FBUE", 2, -1, (1 << 18) - 1, true },
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{ "FBGE", 2, -1, (1 << 18) - 1, true },
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{ "FBUGE", 2, -1, (1 << 18) - 1, true },
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{ "FBLE", 2, -1, (1 << 18) - 1, true },
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{ "FBULE", 2, -1, (1 << 18) - 1, true },
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{ "FBO", 2, -1, (1 << 18) - 1, true },
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// Load integer instructions
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{ "LDSB", 3, 2, (1 << 12) - 1, true },
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{ "LDSH", 3, 2, (1 << 12) - 1, true },
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{ "LDSW", 3, 2, (1 << 12) - 1, true },
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{ "LDUB", 3, 2, (1 << 12) - 1, true },
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{ "LDUH", 3, 2, (1 << 12) - 1, true },
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{ "LDUW", 3, 2, (1 << 12) - 1, true },
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{ "LDX", 3, 2, (1 << 12) - 1, true },
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// Load floating-point instructions
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{ "LD", 3, 2, (1 << 12) - 1, true },
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{ "LDD", 3, 2, (1 << 12) - 1, true },
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{ "LDQ", 3, 2, (1 << 12) - 1, true },
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// Store integer instructions
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{ "STB", 3, -1, (1 << 12) - 1, true },
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{ "STH", 3, -1, (1 << 12) - 1, true },
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{ "STW", 3, -1, (1 << 12) - 1, true },
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{ "STX", 3, -1, (1 << 12) - 1, true },
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// Store floating-point instructions
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{ "ST", 3, -1, (1 << 12) - 1, true },
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{ "STD", 3, -1, (1 << 12) - 1, true },
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// Call, Return and "Jump and link"
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{ "CALL", 1, -1, (1 << 29) - 1, true },
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{ "JMPL", 3, -1, (1 << 12) - 1, true },
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{ "RETURN", 2, -1, 0, false },
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// End-of-array marker
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{ "INVALID_SPARC_OPCODE", 0, -1, 0, false }
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};
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/***************************************************************************/
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#endif
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