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[Hexagon] Simplifying some store patterns. Adding AddrGP addressing forms.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228220 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-02-04 22:36:28 +00:00
parent cec4461c47
commit 243f011835
3 changed files with 16 additions and 24 deletions
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5
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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@ -79,6 +79,7 @@ public:
// Complex Pattern Selectors.
inline bool SelectAddrGA(SDValue &N, SDValue &R);
inline bool SelectAddrGP(SDValue &N, SDValue &R);
bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
bool SelectAddrFI(SDValue &N, SDValue &R);
@ -1637,6 +1638,10 @@ inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) {
return SelectGlobalAddress(N, R, false);
}
inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) {
return SelectGlobalAddress(N, R, true);
}
bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
bool UseGP) {
switch (N.getOpcode()) {

34
lib/Target/Hexagon/HexagonInstrInfoV4.td
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@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
def addrga: PatLeaf<(i32 AddrGA:$Addr)>;
def addrgp: PatLeaf<(i32 AddrGP:$Addr)>;
let hasSideEffects = 0 in
class T_Immext<Operand ImmType>
@ -3648,6 +3649,9 @@ class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod,
InstHexagon MI>
: Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>;
class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI>
: Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>;
let Predicates = [HasV4T], AddedComplexity = 30 in {
def : Pat<(truncstorei8 (i32 IntRegs:$src1),
(HexagonCONST32 tglobaladdr:$absaddr)),
@ -4050,6 +4054,12 @@ let AddedComplexity = 120 in {
def: Loadam_pat<sextloadi32, i64, addrga, Sext64, L4_loadri_abs>;
def: Loadam_pat<zextloadi32, i64, addrga, Zext64, L4_loadri_abs>;
}
let AddedComplexity = 100 in {
def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbabs>;
def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhabs>;
def: Storea_pat<store, I32, addrgp, S2_storeriabs>;
def: Storea_pat<store, I64, addrgp, S2_storerdabs>;
}
// Indexed store double word - global address.
// memw(Rs+#u6:2)=#S8
@ -4060,44 +4070,20 @@ def STrih_offset_ext_V4 : STInst<(outs),
[(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
(add IntRegs:$src1, u6_1ImmPred:$src2))]>,
Requires<[HasV4T]>;
// Map from store(globaladdress + x) -> memd(#foo + x)
let AddedComplexity = 100 in
def : Pat<(store (i64 DoubleRegs:$src1),
FoldGlobalAddrGP:$addr),
(S2_storerdabs FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
Requires<[HasV4T]>;
def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
(i64 DoubleRegs:$src1)),
(S2_storerdabs FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
Requires<[HasV4T]>;
// Map from store(globaladdress + x) -> memb(#foo + x)
let AddedComplexity = 100 in
def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
(S2_storerbabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
(S2_storerbabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
// Map from store(globaladdress + x) -> memh(#foo + x)
let AddedComplexity = 100 in
def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
(S2_storerhabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
(S2_storerhabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
// Map from store(globaladdress + x) -> memw(#foo + x)
let AddedComplexity = 100 in
def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
(S2_storeriabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
(S2_storeriabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
Requires<[HasV4T]>;

1
lib/Target/Hexagon/HexagonOperands.td
View File

@ -830,6 +830,7 @@ def AddrFI : ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>;
// folding will happen during DAG combining. For distinguishing between GA
// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used.
def AddrGA : ComplexPattern<i32, 1, "SelectAddrGA", [], []>;
def AddrGP : ComplexPattern<i32, 1, "SelectAddrGP", [], []>;
// Addressing modes.