6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-14 17:34:41 +00:00
Code Issues Projects Releases Wiki Activity

Implement some feedback from sabre

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25946 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2006-02-03 22:38:07 +00:00
parent de99629e2a
commit 244d1dccd1
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -135,14 +135,14 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
/// set operation such as a sign extend or or/xor with constant whose only /// set operation such as a sign extend or or/xor with constant whose only
/// use is Op. If it returns true, the old node that sets bits which are /// use is Op. If it returns true, the old node that sets bits which are
/// not demanded is returned in Old, and its replacement node is returned in /// not demanded is returned in Old, and its replacement node is returned in
/// New, such that callers of SetBitsAreZero may call CombineTo on them if /// New, such that callers of DemandedBitsAreZero may call CombineTo on them if
/// desired. /// desired.
bool TargetLowering::DemandedBitsAreZero(const SDOperand &Op, uint64_t Mask, bool TargetLowering::DemandedBitsAreZero(const SDOperand &Op, uint64_t Mask,
SDOperand &Old, SDOperand &New, SDOperand &Old, SDOperand &New,
SelectionDAG &DAG) { SelectionDAG &DAG) {
// If the operation has more than one use, we're not interested in it. // If the operation has more than one use, we're not interested in it.
// Tracking down and checking all uses would be problematic and slow. // Tracking down and checking all uses would be problematic and slow.
if (!Op.hasOneUse()) if (!Op.Val->hasOneUse())
return false; return false;
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
@ -164,11 +164,11 @@ bool TargetLowering::DemandedBitsAreZero(const SDOperand &Op, uint64_t Mask,
MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
unsigned ExtendBits = MVT::getSizeInBits(EVT); unsigned ExtendBits = MVT::getSizeInBits(EVT);
// If we're extending from something smaller than MVT::i64 and all of the // If we're extending from something smaller than MVT::i64 and all of the
// sign extension bits are masked, return true and set New to be a zero // sign extension bits are masked, return true and set New to be the
// extend inreg from the same type. // first operand, since we no longer care what the high bits are.
if (ExtendBits < 64 && ((Mask & (~0ULL << ExtendBits)) == 0)) { if (ExtendBits < 64 && ((Mask & (~0ULL << ExtendBits)) == 0)) {
Old = Op; Old = Op;
New = DAG.getZeroExtendInReg(Op.getOperand(0), EVT); New = Op.getOperand(0);
return true; return true;
} }
break; break;