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Add some more 64 bit instructions we need for the PowerPC-64 ISel to the tablegen files

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15710 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2004-08-13 02:19:26 +00:00
parent c24b75870b
commit 244e64ead2
2 changed files with 57 additions and 2 deletions
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48
lib/Target/PowerPC/PPCInstrFormats.td
View File

@ -37,6 +37,7 @@ def Spr : Format<19>;
def Sgr : Format<20>;
def Imm15 : Format<21>;
def Vpr : Format<22>;
def Imm6 : Format<23>;
//===----------------------------------------------------------------------===//
//
@ -266,6 +267,7 @@ class XForm_base_r3xo<string name, bits<6> opcode, bits<10> xo, bit rc,
let Inst{31} = rc;
}
class XForm_1<string name, bits<6> opcode, bits<10> xo, bit ppc64,
bit vmx> : XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx>;
@ -448,6 +450,28 @@ class XFXForm_7_ext<string name, bits<6> opcode, bits<10> xo, bits<10> spr,
let SPR = spr;
}
// 1.7.10 XS-Form
class XSForm_1<string name, bits<6> opcode, bits<9> xo, bit rc,
bit ppc64, bit vmx> : I<name, opcode, ppc64, vmx> {
field bits<5> RS;
field bits<5> A;
field bits<6> SH;
let ArgCount = 3;
let Arg0Type = Gpr.Value;
let Arg1Type = Gpr.Value;
let Arg2Type = Imm6.Value;
let Arg3Type = 0;
let Arg4Type = 0;
let Inst{6-10} = RS;
let Inst{11-15} = A;
let Inst{16-20} = SH{1-5};
let Inst{21-29} = xo;
let Inst{30} = SH{0};
let Inst{31} = rc;
}
// 1.7.11 XO-Form
class XOForm_1<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc,
bit ppc64, bit vmx> : I<name, opcode, ppc64, vmx> {
@ -563,6 +587,30 @@ class MForm_2<string name, bits<6> opcode, bit rc, bit ppc64, bit vmx>
let Arg2Type = Imm5.Value;
}
// 1.7.14 MD-Form
class MDForm_1<string name, bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit vmx>
: I<name, opcode, ppc64, vmx> {
let ArgCount = 4;
field bits<5> RS;
field bits<5> RA;
field bits<6> SH;
field bits<6> MBE;
let Arg0Type = Gpr.Value;
let Arg1Type = Gpr.Value;
let Arg2Type = Imm6.Value;
let Arg3Type = Imm6.Value;
let Arg4Type = 0;
let Inst{6-10} = RS;
let Inst{11-15} = RA;
let Inst{16-20} = SH{1-5};
let Inst{21-26} = MBE;
let Inst{27-29} = xo;
let Inst{30} = SH{0};
let Inst{31} = rc;
}
//===----------------------------------------------------------------------===//
class Pseudo<string name> : I<name, 0, 0, 0> {

11
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -123,6 +123,7 @@ def MFLR : XFXForm_1_ext<"mflr", 31, 399, 8, 0, 0>;
def MFCTR : XFXForm_1_ext<"mfctr", 31, 399, 9, 0, 0>;
def MTLR : XFXForm_7_ext<"mtlr", 31, 467, 8, 0, 0>;
def MTCTR : XFXForm_7_ext<"mtctr", 31, 467, 9, 0, 0>;
def MULLD : XOForm_1<"mulld", 31, 233, 0, 0, 1, 0>;
def MULLW : XOForm_1<"mullw", 31, 235, 0, 0, 0, 0>;
def MULHWU : XOForm_2<"mulhwu", 31, 11, 0, 0, 0>;
def NAND : XForm_6<"nand", 31, 476, 0, 0, 0>;
@ -133,13 +134,19 @@ def ORI : DForm_4<"ori", 24, 0, 0>;
def ORIS : DForm_4<"oris", 25, 0, 0>;
def OR : XForm_6<"or", 31, 444, 0, 0, 0>;
def ORo : XForm_6<"or.", 31, 444, 1, 0, 0>;
def RLDICL : MDForm_1<"rldicl", 30, 0, 0, 1, 0>;
def RLDICR : MDForm_1<"rldicr", 30, 1, 0, 1, 0>;
def RLWINM : MForm_2<"rlwinm", 21, 0, 0, 0>;
def RLWNM : MForm_1<"rlwnm", 23, 0, 0, 0>;
def RLWIMI : MForm_2<"rlwimi", 20, 0, 0, 0>;
def SLD : XForm_6<"sld", 31, 27, 0, 1, 0>;
def SLW : XForm_6<"slw", 31, 24, 0, 0, 0>;
def SRW : XForm_6<"srw", 31, 24, 0, 0, 0>;
def SRD : XForm_6<"srd", 31, 539, 0, 1, 0>;
def SRW : XForm_6<"srw", 31, 536, 0, 0, 0>;
def SRADI : XSForm_1<"sradi", 31, 413, 0, 1, 0>;
def SRAWI : XForm_10<"srawi", 31, 824, 0, 0, 0>;
def SRAW : XForm_6<"sraw", 31, 280, 0, 0, 0>;
def SRAD : XForm_6<"srad", 31, 794, 0, 1, 0>;
def SRAW : XForm_6<"sraw", 31, 792, 0, 0, 0>;
def STB : DForm_3<"stb", 38, 0, 0>;
def STBU : DForm_3<"stbu", 39, 0, 0>;
def STBX : XForm_8<"stbx", 31, 215, 0, 0>;