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Should also check SMLAD for invalid register values.

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rdar://problem/9246650


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129042 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-07 00:50:25 +00:00
parent ae6c95b58e
commit 2455268cdd
2 changed files with 23 additions and 6 deletions
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18
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -536,18 +536,22 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) {
return false; return false;
case ARM::MLA: case ARM::MLS: case ARM::SMLABB: case ARM::SMLABT: case ARM::MLA: case ARM::MLS: case ARM::SMLABB: case ARM::SMLABT:
case ARM::SMLATB: case ARM::SMLATT: case ARM::SMLAWB: case ARM::SMLAWT: case ARM::SMLATB: case ARM::SMLATT: case ARM::SMLAWB: case ARM::SMLAWT:
case ARM::SMMLA: case ARM::SMMLS: case ARM::SMLSD: case ARM::SMLSDX: case ARM::SMMLA: case ARM::SMMLS:
if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15) if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15)
return true; return true;
return false; return false;
case ARM::MUL: case ARM::SMMUL: case ARM::SMULBB: case ARM::SMULBT: case ARM::MUL: case ARM::SMMUL: case ARM::SMULBB: case ARM::SMULBT:
case ARM::SMULTB: case ARM::SMULTT: case ARM::SMULWB: case ARM::SMULWT: case ARM::SMULTB: case ARM::SMULTT: case ARM::SMULWB: case ARM::SMULWT:
case ARM::SMUAD: case ARM::SMUADX:
// A8.6.167 SMLAD & A8.6.172 SMLSD
case ARM::SMLAD: case ARM::SMLADX: case ARM::SMLSD: case ARM::SMLSDX:
if (R19_16 == 15 || R11_8 == 15 || R3_0 == 15) if (R19_16 == 15 || R11_8 == 15 || R3_0 == 15)
return true; return true;
return false; return false;
case ARM::SMLAL: case ARM::SMULL: case ARM::UMAAL: case ARM::UMLAL: case ARM::SMLAL: case ARM::SMULL: case ARM::UMAAL: case ARM::UMLAL:
case ARM::UMULL: case ARM::SMLALBB: case ARM::SMLALBT: case ARM::SMLALTB: case ARM::UMULL:
case ARM::SMLALTT: case ARM::SMLSLD: case ARM::SMLSLDX: case ARM::SMLALBB: case ARM::SMLALBT: case ARM::SMLALTB: case ARM::SMLALTT:
case ARM::SMLALD: case ARM::SMLALDX: case ARM::SMLSLD: case ARM::SMLSLDX:
if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15) if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15)
return true; return true;
if (R19_16 == R15_12) if (R19_16 == R15_12)
@ -558,14 +562,16 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) {
// Multiply Instructions. // Multiply Instructions.
// MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS, // MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS,
// SMLSD, SMLSDX: // SMLAD, SMLADX, SMLSD, SMLSDX:
// Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12} // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12}
// But note that register checking for {SMLAD, SMLADX, SMLSD, SMLSDX} is
// only for {d, n, m}.
// //
// MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT: // MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMUAD, SMUADX:
// Rd{19-16} Rn{3-0} Rm{11-8} // Rd{19-16} Rn{3-0} Rm{11-8}
// //
// SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT,
// SMLSLD // SMLALD, SMLADLX, SMLSLD, SMLSLDX:
// RdLo{15-12} RdHi{19-16} Rn{3-0} Rm{11-8} // RdLo{15-12} RdHi{19-16} Rn{3-0} Rm{11-8}
// //
// The mapping of the multiply registers to the "regular" ARM registers, where // The mapping of the multiply registers to the "regular" ARM registers, where

11
test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt Normal file
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@ -0,0 +1,11 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1|
# -------------------------------------------------------------------------------------------------
#
# A8.6.167
# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE
0x1b 0x68 0xf 0x97