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[AArch64] Refactor the NEON signed/unsigned floating-point convert to fixed-point

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LLVM AArch64 intrinsics to use f32/f64, rather than their vector equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196964 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2013-12-10 21:33:56 +00:00
parent c000d11d5d
commit 2456ea5c92
3 changed files with 12 additions and 16 deletions
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4
include/llvm/IR/IntrinsicsAArch64.td
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@ -358,11 +358,11 @@ def int_aarch64_neon_vcvtfxu2fp_n :
// Scalar Floating-point Convert To Signed Fixed-point (Immediate) // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
def int_aarch64_neon_vcvtfp2fxs_n : def int_aarch64_neon_vcvtfp2fxs_n :
Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty], [IntrNoMem]>; Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
// Scalar Floating-point Convert To Unsigned Fixed-point (Immediate) // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
def int_aarch64_neon_vcvtfp2fxu_n : def int_aarch64_neon_vcvtfp2fxu_n :
Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty], [IntrNoMem]>; Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
class Neon_SHA_Intrinsic class Neon_SHA_Intrinsic
: Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v1i32_ty, llvm_v4i32_ty], : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v1i32_ty, llvm_v4i32_ty],

4
lib/Target/AArch64/AArch64InstrNEON.td
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@ -4639,9 +4639,9 @@ multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator opnode,
multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator opnode, multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator opnode,
Instruction INSTS, Instruction INSTS,
Instruction INSTD> { Instruction INSTD> {
def ssi : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn), (i32 shr_imm32:$Imm))), def ssi : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
(INSTS FPR32:$Rn, imm:$Imm)>; (INSTS FPR32:$Rn, imm:$Imm)>;
def ddi : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))), def ddi : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
(INSTD FPR64:$Rn, imm:$Imm)>; (INSTD FPR64:$Rn, imm:$Imm)>;
} }

20
test/CodeGen/AArch64/neon-scalar-cvt.ll
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@ -92,46 +92,42 @@ define i32 @test_vcvts_n_s32_f32(float %a) {
; CHECK: test_vcvts_n_s32_f32 ; CHECK: test_vcvts_n_s32_f32
; CHECK: fcvtzs {{s[0-9]+}}, {{s[0-9]+}}, #1 ; CHECK: fcvtzs {{s[0-9]+}}, {{s[0-9]+}}, #1
entry: entry:
%fcvtzs = insertelement <1 x float> undef, float %a, i32 0 %fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.f32(float %a, i32 1)
%fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.v1f32(<1 x float> %fcvtzs, i32 1)
%0 = extractelement <1 x i32> %fcvtzs1, i32 0 %0 = extractelement <1 x i32> %fcvtzs1, i32 0
ret i32 %0 ret i32 %0
} }
declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.v1f32(<1 x float>, i32) declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.f32(float, i32)
define i64 @test_vcvtd_n_s64_f64(double %a) { define i64 @test_vcvtd_n_s64_f64(double %a) {
; CHECK: test_vcvtd_n_s64_f64 ; CHECK: test_vcvtd_n_s64_f64
; CHECK: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}, #1 ; CHECK: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}, #1
entry: entry:
%fcvtzs = insertelement <1 x double> undef, double %a, i32 0 %fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.f64(double %a, i32 1)
%fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.v1f64(<1 x double> %fcvtzs, i32 1)
%0 = extractelement <1 x i64> %fcvtzs1, i32 0 %0 = extractelement <1 x i64> %fcvtzs1, i32 0
ret i64 %0 ret i64 %0
} }
declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.v1f64(<1 x double>, i32) declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.f64(double, i32)
define i32 @test_vcvts_n_u32_f32(float %a) { define i32 @test_vcvts_n_u32_f32(float %a) {
; CHECK: test_vcvts_n_u32_f32 ; CHECK: test_vcvts_n_u32_f32
; CHECK: fcvtzu {{s[0-9]+}}, {{s[0-9]+}}, #32 ; CHECK: fcvtzu {{s[0-9]+}}, {{s[0-9]+}}, #32
entry: entry:
%fcvtzu = insertelement <1 x float> undef, float %a, i32 0 %fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.f32(float %a, i32 32)
%fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.v1f32(<1 x float> %fcvtzu, i32 32)
%0 = extractelement <1 x i32> %fcvtzu1, i32 0 %0 = extractelement <1 x i32> %fcvtzu1, i32 0
ret i32 %0 ret i32 %0
} }
declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.v1f32(<1 x float>, i32) declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.f32(float, i32)
define i64 @test_vcvtd_n_u64_f64(double %a) { define i64 @test_vcvtd_n_u64_f64(double %a) {
; CHECK: test_vcvtd_n_u64_f64 ; CHECK: test_vcvtd_n_u64_f64
; CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}, #64 ; CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}, #64
entry: entry:
%fcvtzu = insertelement <1 x double> undef, double %a, i32 0 %fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.f64(double %a, i32 64)
%fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.v1f64(<1 x double> %fcvtzu, i32 64)
%0 = extractelement <1 x i64> %fcvtzu1, i32 0 %0 = extractelement <1 x i64> %fcvtzu1, i32 0
ret i64 %0 ret i64 %0
} }
declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.v1f64(<1 x double>, i32) declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.f64(double, i32)