From 248e6c328c06afc2a6af6b95a1a8a41c1b53055c Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Fri, 22 Jul 2011 18:04:48 +0000 Subject: [PATCH] ARM encoding and assembly parsing tests. Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135780 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/ARM/basic-arm-instructions.s | 47 ++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 00087f3a667..42a60a463fa 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1313,6 +1313,53 @@ _func: selne r9, r2, r1 @ encoding: [0xb1,0x9f,0x82,0x16] +@------------------------------------------------------------------------------ +@ SEV +@------------------------------------------------------------------------------ + sev + seveq + +@ CHECK: sev @ encoding: [0x04,0xf0,0x20,0xe3] +@ CHECK: seveq @ encoding: [0x04,0xf0,0x20,0x03] + +@------------------------------------------------------------------------------ +@ SHADD16/SHADD8 +@------------------------------------------------------------------------------ + shadd16 r4, r8, r2 + shadd16gt r4, r8, r2 + shadd8 r4, r8, r2 + shadd8gt r4, r8, r2 + +@ CHECK: shadd16 r4, r8, r2 @ encoding: [0x12,0x4f,0x38,0xe6] +@ CHECK: shadd16gt r4, r8, r2 @ encoding: [0x12,0x4f,0x38,0xc6] +@ CHECK: shadd8 r4, r8, r2 @ encoding: [0x92,0x4f,0x38,0xe6] +@ CHECK: shadd8gt r4, r8, r2 @ encoding: [0x92,0x4f,0x38,0xc6] + + +@------------------------------------------------------------------------------ +@ SHASX +@------------------------------------------------------------------------------ + shasx r4, r8, r2 + shasxgt r4, r8, r2 + +@ CHECK: shasx r4, r8, r2 @ encoding: [0x32,0x4f,0x38,0xe6] +@ CHECK: shasxgt r4, r8, r2 @ encoding: [0x32,0x4f,0x38,0xc6] + + +@------------------------------------------------------------------------------ +@ SHSUB16/SHSUB8 +@------------------------------------------------------------------------------ + shsub16 r4, r8, r2 + shsub16gt r4, r8, r2 + shsub8 r4, r8, r2 + shsub8gt r4, r8, r2 + +@ CHECK: shsub16 r4, r8, r2 @ encoding: [0x72,0x4f,0x38,0xe6] +@ CHECK: shsub16gt r4, r8, r2 @ encoding: [0x72,0x4f,0x38,0xc6] +@ CHECK: shsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xe6] +@ CHECK: shsub8gt r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xc6] + + @------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------