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https://github.com/c64scene-ar/llvm-6502.git
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Support building non-PIC
Remove the LoadHiAddr pseudo-instruction. Optimization of stores to and loads from statics. Force JIT to use new non-PIC codepaths. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22494 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
2130c08930
commit
2497e6391f
@ -28,6 +28,9 @@ FunctionPass *createPPC32ISelPattern(TargetMachine &TM);
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FunctionPass *createPPC64ISelPattern(TargetMachine &TM);
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FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);
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FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM);
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extern bool GPOPT;
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extern bool PICEnabled;
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} // end namespace llvm;
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// GCC #defines PPC on Linux but we use it as our namespace name
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@ -685,7 +685,7 @@ void PPC32ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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unsigned Reg1 = makeAnotherReg(Type::IntTy);
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unsigned Opcode = (Ty == Type::FloatTy) ? PPC::LFS : PPC::LFD;
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// Move value at base + distance into return reg
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BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, Reg1)
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BuildMI(*MBB, IP, PPC::ADDIS, 2, Reg1)
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.addReg(getGlobalBaseReg()).addConstantPoolIndex(CPI);
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BuildMI(*MBB, IP, Opcode, 2, R).addConstantPoolIndex(CPI).addReg(Reg1);
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} else if (isa<ConstantPointerNull>(C)) {
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@ -696,7 +696,7 @@ void PPC32ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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unsigned TmpReg = makeAnotherReg(GV->getType());
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// Move value at base + distance into return reg
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BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, TmpReg)
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BuildMI(*MBB, IP, PPC::ADDIS, 2, TmpReg)
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.addReg(getGlobalBaseReg()).addGlobalAddress(GV);
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if (GV->hasWeakLinkage() || GV->isExternal()) {
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@ -563,7 +563,7 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
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MachineConstantPool *CP = BB->getParent()->getConstantPool();
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ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, doubleVal);
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unsigned CPI = CP->getConstantPoolIndex(CFP);
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BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
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BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
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.addConstantPoolIndex(CPI);
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BuildMI(BB, PPC::LFD, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
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return Result;
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@ -909,7 +909,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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// Load constant fp value
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unsigned Tmp4 = MakeReg(MVT::i32);
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unsigned TmpL = MakeReg(MVT::i32);
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BuildMI(BB, PPC::LOADHiAddr, 2, Tmp4).addReg(getGlobalBaseReg())
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BuildMI(BB, PPC::ADDIS, 2, Tmp4).addReg(getGlobalBaseReg())
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.addConstantPoolIndex(CPI);
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BuildMI(BB, PPC::LFD, 2, ConstF).addConstantPoolIndex(CPI).addReg(Tmp4);
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// Store the hi & low halves of the fp value, currently in int regs
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@ -1002,7 +1002,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::ConstantPool:
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Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
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Tmp2 = MakeReg(MVT::i64);
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BuildMI(BB, PPC::LOADHiAddr, 2, Tmp2).addReg(getGlobalBaseReg())
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BuildMI(BB, PPC::ADDIS, 2, Tmp2).addReg(getGlobalBaseReg())
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.addConstantPoolIndex(Tmp1);
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BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp2).addConstantPoolIndex(Tmp1);
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return Result;
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@ -1015,7 +1015,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::GlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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Tmp1 = MakeReg(MVT::i64);
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BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
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BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
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.addGlobalAddress(GV);
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if (GV->hasWeakLinkage() || GV->isExternal()) {
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BuildMI(BB, PPC::LD, 2, Result).addGlobalAddress(GV).addReg(Tmp1);
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@ -1057,7 +1057,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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Tmp1 = MakeReg(MVT::i64);
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int CPI = CP->getIndex();
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BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
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BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
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.addConstantPoolIndex(CPI);
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BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
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}
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@ -135,21 +135,28 @@ namespace {
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}
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void printSymbolHi(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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O << "ha16(";
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printOp(MI->getOperand(OpNo));
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O << "-\"L0000" << LabelNumber << "$pb\")";
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if (MI->getOperand(OpNo).isImmediate()) {
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printS16ImmOperand(MI, OpNo, VT);
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} else {
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O << "ha16(";
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printOp(MI->getOperand(OpNo));
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if (PICEnabled)
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O << "-\"L0000" << LabelNumber << "$pb\")";
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else
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O << ')';
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}
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}
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void printSymbolLo(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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// FIXME: Because LFS, LFD, and LWZ can be used either with a s16imm or
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// a lo16 of a global or constant pool operand, we must handle both here.
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// this isn't a great design, but it works for now.
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if (MI->getOperand(OpNo).isImmediate()) {
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O << (short)MI->getOperand(OpNo).getImmedValue();
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printS16ImmOperand(MI, OpNo, VT);
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} else {
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O << "lo16(";
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printOp(MI->getOperand(OpNo));
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O << "-\"L0000" << LabelNumber << "$pb\")";
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if (PICEnabled)
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O << "-\"L0000" << LabelNumber << "$pb\")";
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else
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O << ')';
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}
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}
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void printcrbit(const MachineInstr *MI, unsigned OpNo,
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@ -428,9 +435,7 @@ void DarwinAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
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}
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bool DarwinAsmPrinter::doInitialization(Module &M) {
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// FIXME: implment subtargets for PowerPC and pick this up from there.
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O << "\t.machine ppc970\n";
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if (GPOPT) O << "\t.machine ppc970\n";
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AsmPrinter::doInitialization(M);
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return false;
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}
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@ -504,6 +509,7 @@ bool DarwinAsmPrinter::doFinalization(Module &M) {
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for (std::set<std::string>::iterator i = FnStubs.begin(), e = FnStubs.end();
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i != e; ++i)
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{
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if (PICEnabled) {
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O << ".data\n";
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O << ".section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32\n";
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emitAlignment(2);
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@ -523,6 +529,20 @@ bool DarwinAsmPrinter::doFinalization(Module &M) {
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O << "L" << *i << "$lazy_ptr:\n";
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O << "\t.indirect_symbol " << *i << "\n";
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O << "\t.long dyld_stub_binding_helper\n";
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} else {
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O << "\t.section __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16\n";
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emitAlignment(4);
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O << "L" << *i << "$stub:\n";
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O << "\t.indirect_symbol " << *i << "\n";
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O << "\tlis r11,ha16(L" << *i << "$lazy_ptr)\n";
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O << "\tlwzu r12,lo16(L" << *i << "$lazy_ptr)(r11)\n";
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O << "\tmtctr r12\n";
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O << "\tbctr\n";
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O << "\t.lazy_symbol_pointer\n";
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O << "L" << *i << "$lazy_ptr:\n";
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O << "\t.indirect_symbol " << *i << "\n";
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O << "\t.long dyld_stub_binding_helper\n";
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}
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}
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O << "\n";
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@ -28,10 +28,6 @@ namespace {
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TargetMachine &TM;
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MachineCodeEmitter &MCE;
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/// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
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/// its address in the function into this pointer.
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void *MovePCtoLROffset;
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// Tracks which instruction references which BasicBlock
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std::vector<std::pair<MachineBasicBlock*, unsigned*> > BBRefs;
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// Tracks where each BasicBlock starts
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@ -87,7 +83,6 @@ bool PPC32TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
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}
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bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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MovePCtoLROffset = 0;
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MCE.startFunction(MF);
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MCE.emitConstantPool(MF.getConstantPool());
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for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
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@ -120,6 +115,7 @@ bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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}
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void PPC32CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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assert(!PICEnabled && "CodeEmitter does not support PIC!");
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BBLocations[&MBB] = MCE.getCurrentPCValue();
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
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MachineInstr &MI = *I;
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@ -131,10 +127,7 @@ void PPC32CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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case PPC::IMPLICIT_DEF:
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break; // pseudo opcode, no side effects
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case PPC::MovePCtoLR:
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assert(MovePCtoLROffset == 0 &&
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"Multiple MovePCtoLR instructions in the function?");
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MovePCtoLROffset = (void*)(intptr_t)MCE.getCurrentPCValue();
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emitWord(0x48000005); // bl 1
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assert(0 && "CodeEmitter does not support MovePCtoLR instruction");
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break;
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}
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}
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@ -200,55 +193,59 @@ int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
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MO.getGlobal()->hasWeakLinkage() ||
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MO.getGlobal()->isExternal();
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unsigned Reloc = 0;
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int Offset = 0;
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if (MI.getOpcode() == PPC::CALLpcrel)
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Reloc = PPC::reloc_pcrel_bx;
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else {
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assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
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Offset = -((intptr_t)MovePCtoLROffset+4);
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if (MI.getOpcode() == PPC::LOADHiAddr) {
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switch (MI.getOpcode()) {
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default: MI.dump(); assert(0 && "Unknown instruction for relocation!");
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case PPC::LIS:
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if (isExternal)
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Reloc = PPC::reloc_absolute_ptr_high; // Pointer to stub
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else
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else
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Reloc = PPC::reloc_absolute_high; // Pointer to symbol
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} else if (MI.getOpcode() == PPC::LA) {
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break;
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case PPC::LA:
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assert(!isExternal && "Something in the ISEL changed\n");
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Reloc = PPC::reloc_absolute_low;
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} else if (MI.getOpcode() == PPC::LWZ) {
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Reloc = PPC::reloc_absolute_ptr_low;
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assert(isExternal && "Something in the ISEL changed\n");
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} else {
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// These don't show up for global value references AFAIK, only for
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// constant pool refs: PPC::LFS, PPC::LFD
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assert(0 && "Unknown instruction for relocation!");
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break;
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case PPC::LBZ:
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case PPC::LHA:
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case PPC::LHZ:
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case PPC::LWZ:
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case PPC::LFS:
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case PPC::LFD:
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case PPC::STB:
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case PPC::STH:
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case PPC::STW:
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case PPC::STFS:
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case PPC::STFD:
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if (isExternal)
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Reloc = PPC::reloc_absolute_ptr_low;
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else
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Reloc = PPC::reloc_absolute_low;
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break;
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}
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}
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if (MO.isGlobalAddress())
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MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
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Reloc, MO.getGlobal(), Offset));
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Reloc, MO.getGlobal(), 0));
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else
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MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
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Reloc, MO.getSymbolName(), Offset));
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Reloc, MO.getSymbolName(), 0));
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} else if (MO.isMachineBasicBlock()) {
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unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
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BBRefs.push_back(std::make_pair(MO.getMachineBasicBlock(), CurrPC));
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} else if (MO.isConstantPoolIndex()) {
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unsigned index = MO.getConstantPoolIndex();
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assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
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rv = MCE.getConstantPoolEntryAddress(index) - (intptr_t)MovePCtoLROffset-4;
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unsigned Opcode = MI.getOpcode();
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if (Opcode == PPC::LOADHiAddr) {
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// LoadHiAddr wants hi16(addr - &MovePCtoLR)
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rv = MCE.getConstantPoolEntryAddress(index);
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if (Opcode == PPC::LIS) {
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// lis wants hi16(addr)
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if ((short)rv < 0) rv += 1 << 16;
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rv >>= 16;
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} else if (Opcode == PPC::LWZ || Opcode == PPC::LA ||
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Opcode == PPC::LFS || Opcode == PPC::LFD) {
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// These load opcodes want lo16(addr - &MovePCtoLR)
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// These load opcodes want lo16(addr)
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rv &= 0xffff;
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} else {
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assert(0 && "Unknown constant pool using instruction!");
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@ -35,11 +35,6 @@
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#include <algorithm>
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using namespace llvm;
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// FIXME: temporary.
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#include "llvm/Support/CommandLine.h"
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static cl::opt<bool> EnableGPOPT("enable-gpopt", cl::Hidden,
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cl::desc("Enable optimizations for GP cpus"));
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//===----------------------------------------------------------------------===//
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// PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
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namespace {
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@ -78,7 +73,7 @@ namespace {
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setOperationAction(ISD::SREM , MVT::f32, Expand);
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// If we're enabling GP optimizations, use hardware square root
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if (!EnableGPOPT) {
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if (!GPOPT) {
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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}
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@ -959,8 +954,11 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
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MachineConstantPool *CP = BB->getParent()->getConstantPool();
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ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, doubleVal);
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unsigned CPI = CP->getConstantPoolIndex(CFP);
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BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
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.addConstantPoolIndex(CPI);
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if (PICEnabled)
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BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
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.addConstantPoolIndex(CPI);
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else
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BuildMI(BB, PPC::LIS, 1, Tmp1).addConstantPoolIndex(CPI);
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BuildMI(BB, PPC::LFD, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
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return Result;
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}
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@ -970,7 +968,7 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
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void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
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unsigned IntCR = MakeReg(MVT::i32);
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BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
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BuildMI(BB, EnableGPOPT ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
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BuildMI(BB, GPOPT ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
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if (Inv) {
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unsigned Tmp1 = MakeReg(MVT::i32);
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BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(32-(3-Idx))
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@ -1359,8 +1357,11 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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case ISD::ConstantPool:
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Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
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Tmp2 = MakeReg(MVT::i32);
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BuildMI(BB, PPC::LOADHiAddr, 2, Tmp2).addReg(getGlobalBaseReg())
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.addConstantPoolIndex(Tmp1);
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if (PICEnabled)
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BuildMI(BB, PPC::ADDIS, 2, Tmp2).addReg(getGlobalBaseReg())
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.addConstantPoolIndex(Tmp1);
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else
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BuildMI(BB, PPC::LIS, 1, Tmp2).addConstantPoolIndex(Tmp1);
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BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp2).addConstantPoolIndex(Tmp1);
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return Result;
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@ -1372,8 +1373,11 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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case ISD::GlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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Tmp1 = MakeReg(MVT::i32);
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BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
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.addGlobalAddress(GV);
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if (PICEnabled)
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BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
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.addGlobalAddress(GV);
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else
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BuildMI(BB, PPC::LIS, 2, Tmp1).addGlobalAddress(GV);
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if (GV->hasWeakLinkage() || GV->isExternal()) {
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BuildMI(BB, PPC::LWZ, 2, Result).addGlobalAddress(GV).addReg(Tmp1);
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} else {
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@ -1413,13 +1417,29 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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Tmp1 = MakeReg(MVT::i32);
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int CPI = CP->getIndex();
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BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
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.addConstantPoolIndex(CPI);
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if (PICEnabled)
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BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
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.addConstantPoolIndex(CPI);
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else
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BuildMI(BB, PPC::LIS, 1, Tmp1).addConstantPoolIndex(CPI);
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BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
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}
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else if(Address.getOpcode() == ISD::FrameIndex) {
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} else if (Address.getOpcode() == ISD::FrameIndex) {
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Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
|
||||
addFrameReference(BuildMI(BB, Opc, 2, Result), (int)Tmp1);
|
||||
} else if(GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Address)){
|
||||
GlobalValue *GV = GN->getGlobal();
|
||||
Tmp1 = MakeReg(MVT::i32);
|
||||
if (PICEnabled)
|
||||
BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
|
||||
.addGlobalAddress(GV);
|
||||
else
|
||||
BuildMI(BB, PPC::LIS, 2, Tmp1).addGlobalAddress(GV);
|
||||
if (GV->hasWeakLinkage() || GV->isExternal()) {
|
||||
Tmp2 = MakeReg(MVT::i32);
|
||||
BuildMI(BB, PPC::LWZ, 2, Tmp2).addGlobalAddress(GV).addReg(Tmp1);
|
||||
Tmp1 = Tmp2;
|
||||
}
|
||||
BuildMI(BB, Opc, 2, Result).addGlobalAddress(GV).addReg(Tmp1);
|
||||
} else {
|
||||
int offset;
|
||||
bool idx = SelectAddr(Address, Tmp1, offset);
|
||||
@ -2344,7 +2364,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
|
||||
}
|
||||
|
||||
void ISel::Select(SDOperand N) {
|
||||
unsigned Tmp1, Tmp2, Opc;
|
||||
unsigned Tmp1, Tmp2, Tmp3, Opc;
|
||||
unsigned opcode = N.getOpcode();
|
||||
|
||||
if (!ExprMap.insert(std::make_pair(N, 1)).second)
|
||||
@ -2432,49 +2452,59 @@ void ISel::Select(SDOperand N) {
|
||||
BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
|
||||
return;
|
||||
case ISD::TRUNCSTORE:
|
||||
case ISD::STORE:
|
||||
{
|
||||
SDOperand Chain = N.getOperand(0);
|
||||
SDOperand Value = N.getOperand(1);
|
||||
SDOperand Address = N.getOperand(2);
|
||||
Select(Chain);
|
||||
case ISD::STORE: {
|
||||
SDOperand Chain = N.getOperand(0);
|
||||
SDOperand Value = N.getOperand(1);
|
||||
SDOperand Address = N.getOperand(2);
|
||||
Select(Chain);
|
||||
|
||||
Tmp1 = SelectExpr(Value); //value
|
||||
Tmp1 = SelectExpr(Value); //value
|
||||
|
||||
if (opcode == ISD::STORE) {
|
||||
switch(Value.getValueType()) {
|
||||
default: assert(0 && "unknown Type in store");
|
||||
case MVT::i32: Opc = PPC::STW; break;
|
||||
case MVT::f64: Opc = PPC::STFD; break;
|
||||
case MVT::f32: Opc = PPC::STFS; break;
|
||||
}
|
||||
} else { //ISD::TRUNCSTORE
|
||||
switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) {
|
||||
default: assert(0 && "unknown Type in store");
|
||||
case MVT::i1:
|
||||
case MVT::i8: Opc = PPC::STB; break;
|
||||
case MVT::i16: Opc = PPC::STH; break;
|
||||
}
|
||||
if (opcode == ISD::STORE) {
|
||||
switch(Value.getValueType()) {
|
||||
default: assert(0 && "unknown Type in store");
|
||||
case MVT::i32: Opc = PPC::STW; break;
|
||||
case MVT::f64: Opc = PPC::STFD; break;
|
||||
case MVT::f32: Opc = PPC::STFS; break;
|
||||
}
|
||||
|
||||
if(Address.getOpcode() == ISD::FrameIndex)
|
||||
{
|
||||
Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
|
||||
addFrameReference(BuildMI(BB, Opc, 3).addReg(Tmp1), (int)Tmp2);
|
||||
} else { //ISD::TRUNCSTORE
|
||||
switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) {
|
||||
default: assert(0 && "unknown Type in store");
|
||||
case MVT::i1:
|
||||
case MVT::i8: Opc = PPC::STB; break;
|
||||
case MVT::i16: Opc = PPC::STH; break;
|
||||
}
|
||||
else
|
||||
{
|
||||
int offset;
|
||||
bool idx = SelectAddr(Address, Tmp2, offset);
|
||||
if (idx) {
|
||||
Opc = IndexedOpForOp(Opc);
|
||||
BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
|
||||
} else {
|
||||
BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
if(Address.getOpcode() == ISD::FrameIndex) {
|
||||
Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
|
||||
addFrameReference(BuildMI(BB, Opc, 3).addReg(Tmp1), (int)Tmp2);
|
||||
} else if(GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Address)){
|
||||
GlobalValue *GV = GN->getGlobal();
|
||||
Tmp2 = MakeReg(MVT::i32);
|
||||
if (PICEnabled)
|
||||
BuildMI(BB, PPC::ADDIS, 2, Tmp2).addReg(getGlobalBaseReg())
|
||||
.addGlobalAddress(GV);
|
||||
else
|
||||
BuildMI(BB, PPC::LIS, 2, Tmp2).addGlobalAddress(GV);
|
||||
if (GV->hasWeakLinkage() || GV->isExternal()) {
|
||||
Tmp3 = MakeReg(MVT::i32);
|
||||
BuildMI(BB, PPC::LWZ, 2, Tmp3).addGlobalAddress(GV).addReg(Tmp2);
|
||||
Tmp2 = Tmp3;
|
||||
}
|
||||
BuildMI(BB, Opc, 3).addReg(Tmp1).addGlobalAddress(GV).addReg(Tmp2);
|
||||
} else {
|
||||
int offset;
|
||||
bool idx = SelectAddr(Address, Tmp2, offset);
|
||||
if (idx) {
|
||||
Opc = IndexedOpForOp(Opc);
|
||||
BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
|
||||
} else {
|
||||
BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
case ISD::EXTLOAD:
|
||||
case ISD::SEXTLOAD:
|
||||
case ISD::ZEXTLOAD:
|
||||
|
||||
@ -108,17 +108,17 @@ let isCall = 1,
|
||||
// register and an immediate are of this type.
|
||||
//
|
||||
let isLoad = 1 in {
|
||||
def LBZ : DForm_1<34, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
|
||||
def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
|
||||
"lbz $rD, $disp($rA)">;
|
||||
def LHA : DForm_1<42, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
|
||||
def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
|
||||
"lha $rD, $disp($rA)">;
|
||||
def LHZ : DForm_1<40, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
|
||||
def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
|
||||
"lhz $rD, $disp($rA)">;
|
||||
def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
|
||||
"lmw $rD, $disp($rA)">;
|
||||
def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
|
||||
"lwz $rD, $disp($rA)">;
|
||||
def LWZU : DForm_1<35, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
|
||||
def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
|
||||
"lwzu $rD, $disp($rA)">;
|
||||
}
|
||||
def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
||||
@ -127,28 +127,26 @@ def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
||||
"addic $rD, $rA, $imm">;
|
||||
def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
||||
"addic. $rD, $rA, $imm">;
|
||||
def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
||||
def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
|
||||
"addis $rD, $rA, $imm">;
|
||||
def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
|
||||
"la $rD, $sym($rA)">;
|
||||
def LOADHiAddr : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
|
||||
"addis $rD, $rA, $sym">;
|
||||
def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
||||
"mulli $rD, $rA, $imm">;
|
||||
def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
||||
"subfic $rD, $rA, $imm">;
|
||||
def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
|
||||
"li $rD, $imm">;
|
||||
def LIS : DForm_2_r0<15, (ops GPRC:$rD, s16imm:$imm),
|
||||
def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
|
||||
"lis $rD, $imm">;
|
||||
let isStore = 1 in {
|
||||
def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
"stmw $rS, $disp($rA)">;
|
||||
def STB : DForm_3<38, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
|
||||
"stb $rS, $disp($rA)">;
|
||||
def STH : DForm_3<44, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
|
||||
"sth $rS, $disp($rA)">;
|
||||
def STW : DForm_3<36, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
|
||||
"stw $rS, $disp($rA)">;
|
||||
def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
"stwu $rS, $disp($rA)">;
|
||||
@ -185,9 +183,9 @@ def LFD : DForm_8<50, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
|
||||
"lfd $rD, $disp($rA)">;
|
||||
}
|
||||
let isStore = 1 in {
|
||||
def STFS : DForm_9<52, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
def STFS : DForm_9<52, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
|
||||
"stfs $rS, $disp($rA)">;
|
||||
def STFD : DForm_9<54, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
def STFD : DForm_9<54, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
|
||||
"stfd $rS, $disp($rA)">;
|
||||
}
|
||||
|
||||
|
||||
@ -29,6 +29,8 @@
|
||||
#include <iostream>
|
||||
using namespace llvm;
|
||||
|
||||
bool llvm::GPOPT = false;
|
||||
|
||||
namespace llvm {
|
||||
cl::opt<bool> AIX("aix",
|
||||
cl::desc("Generate AIX/xcoff instead of Darwin/MachO"),
|
||||
@ -36,6 +38,9 @@ namespace llvm {
|
||||
cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc",
|
||||
cl::desc("Enable LSR for PPC (beta)"),
|
||||
cl::Hidden);
|
||||
cl::opt<bool, true> EnableGPOPT("enable-gpopt", cl::Hidden,
|
||||
cl::location(GPOPT),
|
||||
cl::desc("Enable optimizations for GP cpus"));
|
||||
}
|
||||
|
||||
namespace {
|
||||
@ -127,8 +132,11 @@ bool PowerPCTargetMachine::addPassesToEmitFile(PassManager &PM,
|
||||
}
|
||||
|
||||
void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
|
||||
bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(&TM));
|
||||
// The JIT does not support or need PIC.
|
||||
PICEnabled = false;
|
||||
|
||||
bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(&TM));
|
||||
|
||||
if (EnablePPCLSR) {
|
||||
PM.add(createLoopStrengthReducePass());
|
||||
PM.add(createCFGSimplificationPass());
|
||||
@ -170,7 +178,7 @@ void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
|
||||
///
|
||||
PPC32TargetMachine::PPC32TargetMachine(const Module &M, IntrinsicLowering *IL)
|
||||
: PowerPCTargetMachine(PPC32ID, IL,
|
||||
TargetData(PPC32ID,false,4,4,8,4,4,4,2,1,1),
|
||||
TargetData(PPC32ID,false,4,4,4,4,4,4,2,1,1),
|
||||
PowerPCFrameInfo(*this, false)), JITInfo(*this) {}
|
||||
|
||||
/// PPC64TargetMachine ctor - Create a LP64 architecture model
|
||||
|
||||
Loading…
Reference in New Issue
Block a user