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1. Redo mips16 instructions to avoid multiple opcodes for same instruction.

Browse Source 
Change these to patterns.
2. Add another 16 instructions.

Patch by Reed Kotler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161272 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2012-08-03 22:57:02 +00:00
parent dcc4436cdd
commit 24e79e55da
21 changed files with 605 additions and 54 deletions
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19
test/CodeGen/Mips/lhu1.ll Normal file
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@@ -0,0 +1,19 @@
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@s = global i16 255, align 2
@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
define i32 @main() nounwind {
entry:
%i = alloca i32, align 4
%0 = load i16* @s, align 2
%conv = zext i16 %0 to i32
; 16: lhu ${{[0-9]+}}, 0(${{[0-9]+}})
store i32 %conv, i32* %i, align 4
%1 = load i32* %i, align 4
%call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1)
ret i32 0
}
declare i32 @printf(i8*, ...)