From 24f554f05277413fd8ec77f80c3241d0298ab57f Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Sun, 11 May 2014 19:29:07 +0000 Subject: [PATCH] Pass the value type to TLI::getRegisterByName We must validate the value type in TLI::getRegisterByName, because if we don't and the wrong type was used with the IR intrinsic, then we'll assert (because we won't be able to find a valid register class with which to construct the requested copy operation). For PPC64, additionally, the type information is necessary to decide between the 64-bit register and the 32-bit subregister. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208508 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetLowering.h | 2 +- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 4 ++-- lib/Target/AArch64/AArch64ISelLowering.cpp | 3 ++- lib/Target/AArch64/AArch64ISelLowering.h | 2 +- lib/Target/ARM/ARMISelLowering.cpp | 3 ++- lib/Target/ARM/ARMISelLowering.h | 2 +- lib/Target/ARM64/ARM64ISelLowering.cpp | 3 ++- lib/Target/ARM64/ARM64ISelLowering.h | 2 +- lib/Target/X86/X86ISelLowering.cpp | 3 ++- lib/Target/X86/X86ISelLowering.h | 2 +- 10 files changed, 15 insertions(+), 11 deletions(-) diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index c03ddbc9632..060dc72421f 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -2217,7 +2217,7 @@ public: /// Return the register ID of the name passed in. Used by named register /// global variables extension. There is no target-independent behaviour /// so the default action is to bail. - virtual unsigned getRegisterByName(const char* RegName) const { + virtual unsigned getRegisterByName(const char* RegName, EVT VT) const { report_fatal_error("Named registers not implemented for this target"); } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 1cbc83a3f65..a5162fad944 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -1813,7 +1813,7 @@ SDNode MDNodeSDNode *MD = dyn_cast(Op->getOperand(0)); const MDString *RegStr = dyn_cast(MD->getMD()->getOperand(0)); unsigned Reg = getTargetLowering()->getRegisterByName( - RegStr->getString().data()); + RegStr->getString().data(), Op->getValueType(0)); SDValue New = CurDAG->getCopyFromReg( CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0)); New->setNodeId(-1); @@ -1826,7 +1826,7 @@ SDNode MDNodeSDNode *MD = dyn_cast(Op->getOperand(1)); const MDString *RegStr = dyn_cast(MD->getMD()->getOperand(0)); unsigned Reg = getTargetLowering()->getRegisterByName( - RegStr->getString().data()); + RegStr->getString().data(), Op->getOperand(2).getValueType()); SDValue New = CurDAG->getCopyToReg( CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2)); New->setNodeId(-1); diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index a016e6e4855..852d324476a 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -2409,7 +2409,8 @@ SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) // FIXME? Maybe this could be a TableGen attribute on some registers and // this table could be generated automatically from RegInfo. -unsigned AArch64TargetLowering::getRegisterByName(const char* RegName) const { +unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, + EVT VT) const { unsigned Reg = StringSwitch(RegName) .Case("sp", AArch64::XSP) .Default(0); diff --git a/lib/Target/AArch64/AArch64ISelLowering.h b/lib/Target/AArch64/AArch64ISelLowering.h index 143c5528ce8..070db94808f 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.h +++ b/lib/Target/AArch64/AArch64ISelLowering.h @@ -350,7 +350,7 @@ public: SDValue PerformDAGCombine(SDNode *N,DAGCombinerInfo &DCI) const override; - unsigned getRegisterByName(const char* RegName) const override; + unsigned getRegisterByName(const char* RegName, EVT VT) const override; /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 702e549e89a..44e52c09f69 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -3925,7 +3925,8 @@ SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { // FIXME? Maybe this could be a TableGen attribute on some registers and // this table could be generated automatically from RegInfo. -unsigned ARMTargetLowering::getRegisterByName(const char* RegName) const { +unsigned ARMTargetLowering::getRegisterByName(const char* RegName, + EVT VT) const { unsigned Reg = StringSwitch(RegName) .Case("sp", ARM::SP) .Default(0); diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 03c2e34df5c..0175c24b735 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -471,7 +471,7 @@ namespace llvm { SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; - unsigned getRegisterByName(const char* RegName) const override; + unsigned getRegisterByName(const char* RegName, EVT VT) const override; /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be diff --git a/lib/Target/ARM64/ARM64ISelLowering.cpp b/lib/Target/ARM64/ARM64ISelLowering.cpp index b422ddcb43d..1d27e86e215 100644 --- a/lib/Target/ARM64/ARM64ISelLowering.cpp +++ b/lib/Target/ARM64/ARM64ISelLowering.cpp @@ -3445,7 +3445,8 @@ SDValue ARM64TargetLowering::LowerFRAMEADDR(SDValue Op, // FIXME? Maybe this could be a TableGen attribute on some registers and // this table could be generated automatically from RegInfo. -unsigned ARM64TargetLowering::getRegisterByName(const char* RegName) const { +unsigned ARM64TargetLowering::getRegisterByName(const char* RegName, + EVT VT) const { unsigned Reg = StringSwitch(RegName) .Case("sp", ARM64::SP) .Default(0); diff --git a/lib/Target/ARM64/ARM64ISelLowering.h b/lib/Target/ARM64/ARM64ISelLowering.h index d7d08fa52f5..7292e06da77 100644 --- a/lib/Target/ARM64/ARM64ISelLowering.h +++ b/lib/Target/ARM64/ARM64ISelLowering.h @@ -411,7 +411,7 @@ private: ConstraintType getConstraintType(const std::string &Constraint) const override; - unsigned getRegisterByName(const char* RegName) const override; + unsigned getRegisterByName(const char* RegName, EVT VT) const override; /// Examine constraint string and operand type and determine a weight value. /// The operand object must already have been set up with the operand type. diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 616171b2b69..7d24e23d089 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -12817,7 +12817,8 @@ SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { // FIXME? Maybe this could be a TableGen attribute on some registers and // this table could be generated automatically from RegInfo. -unsigned X86TargetLowering::getRegisterByName(const char* RegName) const { +unsigned X86TargetLowering::getRegisterByName(const char* RegName, + EVT VT) const { unsigned Reg = StringSwitch(RegName) .Case("esp", X86::ESP) .Case("rsp", X86::RSP) diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index ff571e47200..7d8a10c187c 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -786,7 +786,7 @@ namespace llvm { return nullptr; // nothing to do, move along. } - unsigned getRegisterByName(const char* RegName) const override; + unsigned getRegisterByName(const char* RegName, EVT VT) const override; /// createFastISel - This method returns a target specific FastISel object, /// or null if the target does not support "fast" ISel.