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[Hexagon] Converting ALU32/ALU intrinsics to new patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226478 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
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@ -13,6 +13,14 @@
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// March 4, 2008
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//===----------------------------------------------------------------------===//
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class T_RI_pat <InstHexagon MI, Intrinsic IntID, PatLeaf ImmPred = PatLeaf<(i32 imm)>>
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: Pat<(IntID I32:$Rs, ImmPred:$It),
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(MI I32:$Rs, ImmPred:$It)>;
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class T_IR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred = PatLeaf<(i32 imm)>>
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: Pat<(IntID ImmPred:$Is, I32:$Rt),
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(MI ImmPred:$Is, I32:$Rt)>;
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class T_RR_pat <InstHexagon MI, Intrinsic IntID>
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: Pat <(IntID I32:$Rs, I32:$Rt),
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(MI I32:$Rs, I32:$Rt)>;
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@ -215,6 +223,20 @@ def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
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def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
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def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
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/********************************************************************
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* ALU32/ALU *
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*********************************************************************/
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def : T_RR_pat<A2_add, int_hexagon_A2_add>;
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def : T_RI_pat<ADD_ri, int_hexagon_A2_addi>;
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def : T_RR_pat<A2_sub, int_hexagon_A2_sub>;
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def : T_IR_pat<SUB_ri, int_hexagon_A2_subri>;
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def : T_RR_pat<A2_and, int_hexagon_A2_and>;
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def : T_RI_pat<AND_ri, int_hexagon_A2_andir>;
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def : T_RR_pat<A2_or, int_hexagon_A2_or>;
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def : T_RI_pat<OR_ri, int_hexagon_A2_orir>;
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def : T_RR_pat<A2_xor, int_hexagon_A2_xor>;
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def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
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//
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// ALU 32 types.
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//
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@ -2045,11 +2067,6 @@ class si_MInst_didi<string opc, Intrinsic IntID>
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
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[(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
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class T_RI_pat <InstHexagon MI, Intrinsic IntID>
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: Pat<(IntID (i32 IntRegs:$Rs), imm:$It),
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(MI IntRegs:$Rs, imm:$It)>;
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//
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// LDInst classes.
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//
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@ -2065,36 +2082,11 @@ class di_LDInstPI_diu4<string opc, Intrinsic IntID>
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* ALU32/ALU *
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*********************************************************************/
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// ALU32 / ALU / Add.
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def HEXAGON_A2_add:
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si_ALU32_sisi <"add", int_hexagon_A2_add>;
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def HEXAGON_A2_addi:
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si_ALU32_sis16 <"add", int_hexagon_A2_addi>;
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// ALU32 / ALU / Logical operations.
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def HEXAGON_A2_and:
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si_ALU32_sisi <"and", int_hexagon_A2_and>;
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def HEXAGON_A2_andir:
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si_ALU32_sis10 <"and", int_hexagon_A2_andir>;
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def HEXAGON_A2_not:
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si_ALU32_si <"not", int_hexagon_A2_not>;
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def HEXAGON_A2_or:
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si_ALU32_sisi <"or", int_hexagon_A2_or>;
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def HEXAGON_A2_orir:
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si_ALU32_sis10 <"or", int_hexagon_A2_orir>;
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def HEXAGON_A2_xor:
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si_ALU32_sisi <"xor", int_hexagon_A2_xor>;
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// ALU32 / ALU / Negate.
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def HEXAGON_A2_neg:
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si_ALU32_si <"neg", int_hexagon_A2_neg>;
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// ALU32 / ALU / Subtract.
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def HEXAGON_A2_sub:
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si_ALU32_sisi <"sub", int_hexagon_A2_sub>;
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def HEXAGON_A2_subri:
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si_ALU32_s10si <"sub", int_hexagon_A2_subri>;
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// ALU32 / ALU / Transfer Immediate.
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def HEXAGON_A2_tfril:
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si_lo_ALU32_siu16 <"", int_hexagon_A2_tfril>;
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119
test/CodeGen/Hexagon/intrinsics-alu32-2.ll
Normal file
119
test/CodeGen/Hexagon/intrinsics-alu32-2.ll
Normal file
@ -0,0 +1,119 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Verify that ALU32 - add, or, and, sub, combine intrinsics
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; are lowered to the right instructions.
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@e = external global i1
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@b = external global i8
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@d = external global i32
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@c = external global i64
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test1(i32 %a, i32 %b) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.add(i32 %a, i32 %b)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}sub(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test2(i32 %a, i32 %b) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.sub(i32 %a, i32 %b)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}and(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test3(i32 %a, i32 %b) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.and(i32 %a, i32 %b)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}or(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test4(i32 %a, i32 %b) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.or(i32 %a, i32 %b)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}xor(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test5(i32 %a, i32 %b) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.xor(i32 %a, i32 %b)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}combine(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test6(i32 %a, i32 %b) #0 {
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entry:
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%0 = tail call i64 @llvm.hexagon.A2.combinew(i32 %a, i32 %b)
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store i64 %0, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}#-31849)
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define void @test7(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.addi(i32 %a, i32 -31849)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}and(r{{[0-9]+}}{{ *}},{{ *}}#-512)
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define void @test8(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.andir(i32 %a, i32 -512)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}or(r{{[0-9]+}}{{ *}},{{ *}}#511)
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define void @test9(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.orir(i32 %a, i32 511)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}sub(#508{{ *}},{{ *}}r{{[0-9]+}})
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define void @test10(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.subri(i32 508, i32 %a)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.A2.add(i32, i32) #1
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declare i32 @llvm.hexagon.A2.sub(i32, i32) #1
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declare i32 @llvm.hexagon.A2.and(i32, i32) #1
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declare i32 @llvm.hexagon.A2.or(i32, i32) #1
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declare i32 @llvm.hexagon.A2.xor(i32, i32) #1
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declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
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declare i32 @llvm.hexagon.A2.addi(i32, i32) #1
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declare i32 @llvm.hexagon.A2.andir(i32, i32) #1
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declare i32 @llvm.hexagon.A2.orir(i32, i32) #1
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declare i32 @llvm.hexagon.A2.subri(i32, i32)
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