From 254d992ab8cbda3b2ef89ca401f5321d5eafe0fb Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Mon, 19 Jan 2015 18:22:19 +0000 Subject: [PATCH] [Hexagon] Converting ALU32/ALU intrinsics to new patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226478 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonIntrinsics.td | 52 ++++----- test/CodeGen/Hexagon/intrinsics-alu32-2.ll | 119 +++++++++++++++++++++ 2 files changed, 141 insertions(+), 30 deletions(-) create mode 100644 test/CodeGen/Hexagon/intrinsics-alu32-2.ll diff --git a/lib/Target/Hexagon/HexagonIntrinsics.td b/lib/Target/Hexagon/HexagonIntrinsics.td index bd108b20952..95d8999766f 100644 --- a/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/lib/Target/Hexagon/HexagonIntrinsics.td @@ -13,6 +13,14 @@ // March 4, 2008 //===----------------------------------------------------------------------===// +class T_RI_pat > + : Pat<(IntID I32:$Rs, ImmPred:$It), + (MI I32:$Rs, ImmPred:$It)>; + +class T_IR_pat > + : Pat<(IntID ImmPred:$Is, I32:$Rt), + (MI ImmPred:$Is, I32:$Rt)>; + class T_RR_pat : Pat <(IntID I32:$Rs, I32:$Rt), (MI I32:$Rs, I32:$Rt)>; @@ -215,6 +223,20 @@ def : T_PRR_pat ; def : T_PRR_pat ; def : T_PRR_pat ; +/******************************************************************** +* ALU32/ALU * +*********************************************************************/ +def : T_RR_pat; +def : T_RI_pat; +def : T_RR_pat; +def : T_IR_pat; +def : T_RR_pat; +def : T_RI_pat; +def : T_RR_pat; +def : T_RI_pat; +def : T_RR_pat; +def : T_RR_pat; + // // ALU 32 types. // @@ -2045,11 +2067,6 @@ class si_MInst_didi !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")), [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>; - -class T_RI_pat - : Pat<(IntID (i32 IntRegs:$Rs), imm:$It), - (MI IntRegs:$Rs, imm:$It)>; - // // LDInst classes. // @@ -2065,36 +2082,11 @@ class di_LDInstPI_diu4 * ALU32/ALU * *********************************************************************/ -// ALU32 / ALU / Add. -def HEXAGON_A2_add: - si_ALU32_sisi <"add", int_hexagon_A2_add>; -def HEXAGON_A2_addi: - si_ALU32_sis16 <"add", int_hexagon_A2_addi>; - -// ALU32 / ALU / Logical operations. -def HEXAGON_A2_and: - si_ALU32_sisi <"and", int_hexagon_A2_and>; -def HEXAGON_A2_andir: - si_ALU32_sis10 <"and", int_hexagon_A2_andir>; -def HEXAGON_A2_not: - si_ALU32_si <"not", int_hexagon_A2_not>; -def HEXAGON_A2_or: - si_ALU32_sisi <"or", int_hexagon_A2_or>; -def HEXAGON_A2_orir: - si_ALU32_sis10 <"or", int_hexagon_A2_orir>; -def HEXAGON_A2_xor: - si_ALU32_sisi <"xor", int_hexagon_A2_xor>; // ALU32 / ALU / Negate. def HEXAGON_A2_neg: si_ALU32_si <"neg", int_hexagon_A2_neg>; -// ALU32 / ALU / Subtract. -def HEXAGON_A2_sub: - si_ALU32_sisi <"sub", int_hexagon_A2_sub>; -def HEXAGON_A2_subri: - si_ALU32_s10si <"sub", int_hexagon_A2_subri>; - // ALU32 / ALU / Transfer Immediate. def HEXAGON_A2_tfril: si_lo_ALU32_siu16 <"", int_hexagon_A2_tfril>; diff --git a/test/CodeGen/Hexagon/intrinsics-alu32-2.ll b/test/CodeGen/Hexagon/intrinsics-alu32-2.ll new file mode 100644 index 00000000000..6fd32e832b0 --- /dev/null +++ b/test/CodeGen/Hexagon/intrinsics-alu32-2.ll @@ -0,0 +1,119 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; Verify that ALU32 - add, or, and, sub, combine intrinsics +; are lowered to the right instructions. + +@e = external global i1 +@b = external global i8 +@d = external global i32 +@c = external global i64 + +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}) + +define void @test1(i32 %a, i32 %b) #0 { +entry: + %0 = tail call i32 @llvm.hexagon.A2.add(i32 %a, i32 %b) + %conv = sext i32 %0 to i64 + store i64 %conv, i64* @c, align 8 + ret void +} + +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}sub(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}) + +define void @test2(i32 %a, i32 %b) #0 { +entry: + %0 = tail call i32 @llvm.hexagon.A2.sub(i32 %a, i32 %b) + %conv = sext i32 %0 to i64 + store i64 %conv, i64* @c, align 8 + ret void +} + +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}and(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}) + +define void @test3(i32 %a, i32 %b) #0 { +entry: + %0 = tail call i32 @llvm.hexagon.A2.and(i32 %a, i32 %b) + %conv = sext i32 %0 to i64 + store i64 %conv, i64* @c, align 8 + ret void +} + +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}or(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}) + +define void @test4(i32 %a, i32 %b) #0 { +entry: + %0 = tail call i32 @llvm.hexagon.A2.or(i32 %a, i32 %b) + %conv = sext i32 %0 to i64 + store i64 %conv, i64* @c, align 8 + ret void +} + +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}xor(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}) + +define void @test5(i32 %a, i32 %b) #0 { +entry: + %0 = tail call i32 @llvm.hexagon.A2.xor(i32 %a, i32 %b) + %conv = sext i32 %0 to i64 + store i64 %conv, i64* @c, align 8 + ret void +} + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}combine(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}) + +define void @test6(i32 %a, i32 %b) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.A2.combinew(i32 %a, i32 %b) + store i64 %0, i64* @c, align 8 + ret void +} + +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}#-31849) + +define void @test7(i32 %a) #0 { +entry: + %0 = tail call i32 @llvm.hexagon.A2.addi(i32 %a, i32 -31849) + %conv = sext i32 %0 to i64 + store i64 %conv, i64* @c, align 8 + ret void +} + +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}and(r{{[0-9]+}}{{ *}},{{ *}}#-512) + +define void @test8(i32 %a) #0 { +entry: + %0 = tail call i32 @llvm.hexagon.A2.andir(i32 %a, i32 -512) + %conv = sext i32 %0 to i64 + store i64 %conv, i64* @c, align 8 + ret void +} + +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}or(r{{[0-9]+}}{{ *}},{{ *}}#511) + +define void @test9(i32 %a) #0 { +entry: + %0 = tail call i32 @llvm.hexagon.A2.orir(i32 %a, i32 511) + %conv = sext i32 %0 to i64 + store i64 %conv, i64* @c, align 8 + ret void +} + +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}sub(#508{{ *}},{{ *}}r{{[0-9]+}}) + +define void @test10(i32 %a) #0 { +entry: + %0 = tail call i32 @llvm.hexagon.A2.subri(i32 508, i32 %a) + %conv = sext i32 %0 to i64 + store i64 %conv, i64* @c, align 8 + ret void +} + +declare i32 @llvm.hexagon.A2.add(i32, i32) #1 +declare i32 @llvm.hexagon.A2.sub(i32, i32) #1 +declare i32 @llvm.hexagon.A2.and(i32, i32) #1 +declare i32 @llvm.hexagon.A2.or(i32, i32) #1 +declare i32 @llvm.hexagon.A2.xor(i32, i32) #1 +declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1 +declare i32 @llvm.hexagon.A2.addi(i32, i32) #1 +declare i32 @llvm.hexagon.A2.andir(i32, i32) #1 +declare i32 @llvm.hexagon.A2.orir(i32, i32) #1 +declare i32 @llvm.hexagon.A2.subri(i32, i32)