6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-01 00:33:09 +00:00
Code Issues Projects Releases Wiki Activity

ARM: remove @llvm.arm.sevl

Browse Source 
This intrinsic is no longer needed with the new @llvm.arm.hint(i32) intrinsic
which provides a generic, extensible manner for adding hint instructions.  This
functionality can now be represented as @llvm.arm.hint(i32 5).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207246 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Saleem Abdulrasool 2014-04-25 17:51:25 +00:00
parent 3bd471dee2
commit 25bc383612
4 changed files with 3 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/IR/IntrinsicsARM.td
View File

@ -122,7 +122,7 @@ def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
//===----------------------------------------------------------------------===//
// HINT
def int_arm_sevl : Intrinsic<[], []>;
def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
//===----------------------------------------------------------------------===//

2
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1841,8 +1841,6 @@ def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
def : Pat<(int_arm_sevl), (HINT 5)>;
def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
"\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
bits<4> Rd;

1
lib/Target/ARM/ARMInstrThumb.td
View File

@ -289,7 +289,6 @@ def : tHintAlias<"sev$p", (tHINT 4, pred:$p)>; // A8.6.157
def : tInstAlias<"sevl$p", (tHINT 5, pred:$p)> {
let Predicates = [IsThumb2, HasV8];
}
def : T2Pat<(int_arm_sevl), (tHINT 5)>;
// The imm operand $val can be used by a debugger to store more information
// about the breakpoint.

4
test/CodeGen/ARM/intrinsics-v8.ll
View File

@ -10,10 +10,10 @@ define void @test() {
; CHECK: dsb ishld
call void @llvm.arm.dsb(i32 9)
; CHECK: sevl
tail call void @llvm.arm.sevl() nounwind
tail call void @llvm.arm.hint(i32 5) nounwind
ret void
}
declare void @llvm.arm.dmb(i32)
declare void @llvm.arm.dsb(i32)
declare void @llvm.arm.sevl() nounwind
declare void @llvm.arm.hint(i32) nounwind