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[C++11] Use 'nullptr' in tablegen output files.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207611 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2014-04-30 05:53:35 +00:00
parent c6b0620101
commit 25d437f45d
3 changed files with 11 additions and 11 deletions
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10
utils/TableGen/InstrInfoEmitter.cpp
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@@ -523,20 +523,20 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
// Emit the implicit uses and defs lists... // Emit the implicit uses and defs lists...
std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
if (UseList.empty()) if (UseList.empty())
OS << "NULL, "; OS << "nullptr, ";
else else
OS << "ImplicitList" << EmittedLists[UseList] << ", "; OS << "ImplicitList" << EmittedLists[UseList] << ", ";
std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
if (DefList.empty()) if (DefList.empty())
OS << "NULL, "; OS << "nullptr, ";
else else
OS << "ImplicitList" << EmittedLists[DefList] << ", "; OS << "ImplicitList" << EmittedLists[DefList] << ", ";
// Emit the operand info. // Emit the operand info.
std::vector<std::string> OperandInfo = GetOperandInfo(Inst); std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
if (OperandInfo.empty()) if (OperandInfo.empty())
OS << "0"; OS << "nullptr";
else else
OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
@@ -548,10 +548,10 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
else if (!Inst.DeprecatedReason.empty()) else if (!Inst.DeprecatedReason.empty())
// Emit the Subtarget feature. // Emit the Subtarget feature.
OS << "," << Target.getInstNamespace() << "::" << Inst.DeprecatedReason OS << "," << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
<< ",0"; << ",nullptr";
else else
// Instruction isn't deprecated. // Instruction isn't deprecated.
OS << ",0,0"; OS << ",0,nullptr";
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
} }

10
utils/TableGen/RegisterInfoEmitter.cpp
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@@ -225,7 +225,7 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
for (unsigned i = 0; i < NumSets; ++i ) { for (unsigned i = 0; i < NumSets; ++i ) {
OS << " \"" << RegBank.getRegSetAt(i).Name << "\",\n"; OS << " \"" << RegBank.getRegSetAt(i).Name << "\",\n";
} }
OS << " 0 };\n" OS << " nullptr };\n"
<< " return PressureNameTable[Idx];\n" << " return PressureNameTable[Idx];\n"
<< "}\n\n"; << "}\n\n";
@@ -1068,7 +1068,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Now that all of the structs have been emitted, emit the instances. // Now that all of the structs have been emitted, emit the instances.
if (!RegisterClasses.empty()) { if (!RegisterClasses.empty()) {
OS << "\nstatic const TargetRegisterClass *const " OS << "\nstatic const TargetRegisterClass *const "
<< "NullRegClasses[] = { NULL };\n\n"; << "NullRegClasses[] = { nullptr };\n\n";
// Emit register class bit mask tables. The first bit mask emitted for a // Emit register class bit mask tables. The first bit mask emitted for a
// register class, RC, is the set of sub-classes, including RC itself. // register class, RC, is the set of sub-classes, including RC itself.
@@ -1135,7 +1135,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< RC.getName() << "Superclasses[] = {\n"; << RC.getName() << "Superclasses[] = {\n";
for (unsigned i = 0; i != Supers.size(); ++i) for (unsigned i = 0; i != Supers.size(); ++i)
OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n"; OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
OS << " NULL\n};\n\n"; OS << " nullptr\n};\n\n";
} }
// Emit methods. // Emit methods.
@@ -1189,7 +1189,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
else else
OS << RC.getName() << "Superclasses,\n "; OS << RC.getName() << "Superclasses,\n ";
if (RC.AltOrderSelect.empty()) if (RC.AltOrderSelect.empty())
OS << "0\n"; OS << "nullptr\n";
else else
OS << RC.getName() << "GetRawAllocationOrder\n"; OS << RC.getName() << "GetRawAllocationOrder\n";
OS << " };\n\n"; OS << " };\n\n";
@@ -1258,7 +1258,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< " if (!Idx) return RC;\n --Idx;\n" << " if (!Idx) return RC;\n --Idx;\n"
<< " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n" << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
<< " unsigned TV = Table[RC->getID()][Idx];\n" << " unsigned TV = Table[RC->getID()][Idx];\n"
<< " return TV ? getRegClass(TV - 1) : 0;\n}\n\n"; << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
} }
EmitRegUnitPressure(OS, RegBank, ClassName); EmitRegUnitPressure(OS, RegBank, ClassName);

2
utils/TableGen/SubtargetEmitter.cpp
View File

@@ -578,7 +578,7 @@ EmitItineraries(raw_ostream &OS,
OS << "\n"; OS << "\n";
OS << "static const llvm::InstrItinerary "; OS << "static const llvm::InstrItinerary ";
if (ItinList.empty()) { if (ItinList.empty()) {
OS << '*' << Name << " = 0;\n"; OS << '*' << Name << " = nullptr;\n";
continue; continue;
} }