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Fix for codegen bug that could cause illegal cmn instruction generation

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In rare cases the dead definition elimination pass code can cause illegal cmn
instructions when it replaces dead registers on instructions that use
unmaterialized frame indexes. This patch disables the dead definition
optimization for instructions which include frame index operands.

rdar://16438284

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206208 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Louis Gerbarg 2014-04-14 21:05:05 +00:00
parent 27539d46cc
commit 261f0df185
2 changed files with 34 additions and 1 deletions
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17
lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
View File

@ -30,7 +30,7 @@ private:
const TargetRegisterInfo *TRI;
bool implicitlyDefinesSubReg(unsigned Reg, const MachineInstr *MI);
bool processMachineBasicBlock(MachineBasicBlock *MBB);
bool usesFrameIndex(const MachineInstr *MI);
public:
static char ID; // Pass identification, replacement for typeid.
explicit ARM64DeadRegisterDefinitions() : MachineFunctionPass(ID) {}
@ -57,12 +57,27 @@ bool ARM64DeadRegisterDefinitions::implicitlyDefinesSubReg(
return false;
}
bool ARM64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr *MI) {
for (int I = MI->getDesc().getNumDefs(), E = MI->getNumOperands(); I != E; ++I) {
if (MI->getOperand(I).isFI())
return true;
}
return false;
}
bool
ARM64DeadRegisterDefinitions::processMachineBasicBlock(MachineBasicBlock *MBB) {
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
++I) {
MachineInstr *MI = I;
if (usesFrameIndex(MI)) {
// We need to skip this instruction because while it appears to have a
// dead def it uses a frame index which might expand into a multi
// instruction sequence during EPI
DEBUG(dbgs() << " Ignoring, operand is frame index\n");
continue;
}
for (int i = 0, e = MI->getDesc().getNumDefs(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isDead() && MO.isDef()) {

18
test/CodeGen/ARM64/dead-def-frame-index.ll Normal file
View File

@ -0,0 +1,18 @@
; RUN: llc -march=arm64 < %s | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios7.0.0"
; Function Attrs: nounwind ssp uwtable
define i32 @test1() #0 {
%tmp1 = alloca i8
%tmp2 = alloca i32, i32 4096
%tmp3 = icmp eq i8* %tmp1, null
%tmp4 = zext i1 %tmp3 to i32
ret i32 %tmp4
; CHECK-LABEL: test1
; CHECK: adds [[TEMP:[a-z0-9]+]], sp, #16384
; CHECK: adds [[TEMP]], [[TEMP]], #15
}