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Teach the DAG->DAG ISel about FNEG, and how it can be used to invert

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several of the PowerPC opcodes that come in both negated and non-negated
forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22845 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-08-17 23:46:35 +00:00
parent 0f66a91721
commit 26653500bb
1 changed files with 29 additions and 2 deletions
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31
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -199,7 +199,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
break; break;
} }
} }
case ISD::ADD: { case ISD::ADD: {
MVT::ValueType Ty = N->getValueType(0); MVT::ValueType Ty = N->getValueType(0);
if (Ty == MVT::i32) { if (Ty == MVT::i32) {
@ -281,7 +280,35 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
Select(N->getOperand(0)), Select(N->getOperand(0)),
Select(N->getOperand(1))); Select(N->getOperand(1)));
break; break;
} }
case ISD::FNEG: {
SDOperand Val = Select(N->getOperand(0));
MVT::ValueType Ty = N->getValueType(0);
if (Val.Val->hasOneUse()) {
unsigned Opc;
switch (Val.getTargetOpcode()) {
default: Opc = 0; break;
case PPC::FABS: Opc = PPC::FNABS; break;
case PPC::FMADD: Opc = PPC::FNMADD; break;
case PPC::FMADDS: Opc = PPC::FNMADDS; break;
case PPC::FMSUB: Opc = PPC::FNMSUB; break;
case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
}
// If we inverted the opcode, then emit the new instruction with the
// inverted opcode and the original instruction's operands. Otherwise,
// fall through and generate a fneg instruction.
if (Opc) {
if (PPC::FNABS == Opc)
CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0));
else
CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0),
Val.getOperand(1), Val.getOperand(2));
break;
}
}
CurDAG->SelectNodeTo(N, Ty, PPC::FNEG, Val);
break;
}
case ISD::RET: { case ISD::RET: {
SDOperand Chain = Select(N->getOperand(0)); // Token chain. SDOperand Chain = Select(N->getOperand(0)); // Token chain.