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Use CodeGenRegister class to make reading in of register information more
systematic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15805 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -103,11 +103,24 @@ Record *CodeGenTarget::getAsmWriter() const {
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return TargetRec->getValueAsDef("AssemblyWriter");
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}
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void CodeGenTarget::ReadRegisters() const {
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std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
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if (Regs.empty())
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throw std::string("No 'Register' subclasses defined!");
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Registers.reserve(Regs.size());
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Registers.assign(Regs.begin(), Regs.end());
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}
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const std::string &CodeGenRegister::getName() const {
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return TheDef->getName();
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}
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void CodeGenTarget::ReadInstructions() const {
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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if (Insts.size() == 0)
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if (Insts.empty())
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throw std::string("No 'Instruction' subclasses defined!");
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std::string InstFormatName =
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@ -17,6 +17,7 @@
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#ifndef CODEGEN_TARGET_H
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#define CODEGEN_TARGET_H
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#include "CodeGenRegisters.h"
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#include "CodeGenInstruction.h"
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#include <iosfwd>
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#include <map>
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@ -25,6 +26,7 @@ namespace llvm {
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class Record;
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class RecordKeeper;
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class CodeGenRegister;
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/// getValueType - Return the MVT::ValueType that the specified TableGen record
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/// corresponds to.
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@ -43,7 +45,9 @@ class CodeGenTarget {
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MVT::ValueType PointerType;
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mutable std::map<std::string, CodeGenInstruction> Instructions;
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mutable std::vector<CodeGenRegister> Registers;
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void ReadInstructions() const;
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void ReadRegisters() const;
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public:
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CodeGenTarget();
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@ -64,8 +68,10 @@ public:
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///
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Record *getAsmWriter() const;
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/// getPHIInstruction - Return the designated PHI instruction.
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const CodeGenInstruction &getPHIInstruction() const;
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const std::vector<CodeGenRegister> &getRegisters() {
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if (Registers.empty()) ReadRegisters();
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return Registers;
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}
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/// getInstructions - Return all of the instructions defined for this target.
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///
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@ -78,6 +84,10 @@ public:
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CodeGenInstruction>::const_iterator inst_iterator;
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inst_iterator inst_begin() const { return getInstructions().begin(); }
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inst_iterator inst_end() const { return Instructions.end(); }
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/// getPHIInstruction - Return the designated PHI instruction.
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///
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const CodeGenInstruction &getPHIInstruction() const;
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};
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} // End llvm namespace
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@ -15,6 +15,7 @@
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#include "RegisterInfoEmitter.h"
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#include "CodeGenTarget.h"
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#include "CodeGenRegisters.h"
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#include "Record.h"
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#include "Support/StringExtras.h"
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#include <set>
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@ -22,12 +23,10 @@ using namespace llvm;
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// runEnums - Print out enum values for all of the registers.
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void RegisterInfoEmitter::runEnums(std::ostream &OS) {
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std::vector<Record*> Registers = Records.getAllDerivedDefinitions("Register");
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CodeGenTarget Target;
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const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
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if (Registers.size() == 0)
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throw std::string("No 'Register' subclasses defined!");
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std::string Namespace = Registers[0]->getValueAsString("Namespace");
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std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
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EmitSourceFileHeader("Target Register Enum Values", OS);
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@ -36,7 +35,7 @@ void RegisterInfoEmitter::runEnums(std::ostream &OS) {
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OS << " enum {\n NoRegister,\n";
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for (unsigned i = 0, e = Registers.size(); i != e; ++i)
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OS << " " << Registers[i]->getName() << ", \t// " << i+1 << "\n";
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OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
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OS << " };\n";
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if (!Namespace.empty())
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@ -46,7 +45,8 @@ void RegisterInfoEmitter::runEnums(std::ostream &OS) {
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void RegisterInfoEmitter::runHeader(std::ostream &OS) {
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EmitSourceFileHeader("Register Information Header Fragment", OS);
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const std::string &TargetName = CodeGenTarget().getName();
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CodeGenTarget Target;
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const std::string &TargetName = Target.getName();
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std::string ClassName = TargetName + "GenRegisterInfo";
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OS << "#include \"llvm/Target/MRegisterInfo.h\"\n\n";
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@ -74,7 +74,6 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) {
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//
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void RegisterInfoEmitter::run(std::ostream &OS) {
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CodeGenTarget Target;
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EmitSourceFileHeader("Register Information Source Fragment", OS);
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// Start out by emitting each of the register classes... to do this, we build
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@ -84,8 +83,6 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
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std::vector<Record*> RegisterClasses =
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Records.getAllDerivedDefinitions("RegisterClass");
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std::vector<Record*> Registers = Records.getAllDerivedDefinitions("Register");
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std::set<Record*> RegistersFound;
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std::vector<std::string> RegClassNames;
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@ -189,18 +186,21 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
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OS << "\n const MRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
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OS << " { \"NOREG\",\t0,\t\t0,\t0 },\n";
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// Now that register alias sets have been emitted, emit the register
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// descriptors now.
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const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
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for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
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Record *Reg = Registers[i];
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const CodeGenRegister &Reg = Registers[i];
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OS << " { \"";
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if (!Reg->getValueAsString("Name").empty())
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OS << Reg->getValueAsString("Name");
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if (!Reg.TheDef->getValueAsString("Name").empty())
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OS << Reg.TheDef->getValueAsString("Name");
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else
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OS << Reg->getName();
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OS << Reg.getName();
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OS << "\",\t";
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if (RegisterAliases.count(Reg))
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OS << Reg->getName() << "_AliasSet,\t";
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if (RegisterAliases.count(Reg.TheDef))
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OS << Reg.getName() << "_AliasSet,\t";
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else
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OS << "Empty_AliasSet,\t";
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OS << "0, 0 },\n";
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