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R600/SI: Fix using wrong operand indices when commuting

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No test since the current SIISelLowering::legalizeOperands
effectively hides this, and the general uses seem to only fire
on SALU instructions which don't have modifiers between
the operands.

When trying to use legalizeOperands immediately after
instruction selection, it now sees a lot more patterns
it did not see before which break on this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218527 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-09-26 17:54:43 +00:00
parent ea849e9adc
commit 26b2a7834e
2 changed files with 23 additions and 14 deletions
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33
lib/Target/R600/SIInstrInfo.cpp
View File

@ -684,19 +684,28 @@ bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
bool NewMI) const {
if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
if (MI->getNumOperands() < 3)
return nullptr;
int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
AMDGPU::OpName::src0);
assert(Src0Idx != -1 && "Should always have src0 operand");
if (!MI->getOperand(Src0Idx).isReg())
return nullptr;
int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
AMDGPU::OpName::src1);
// Make sure it s legal to commute operands for VOP2.
if (isVOP2(MI->getOpcode()) &&
(!isOperandLegal(MI, 1, &MI->getOperand(2)) ||
!isOperandLegal(MI, 2, &MI->getOperand(1))))
if ((Src1Idx != -1) && isVOP2(MI->getOpcode()) &&
(!isOperandLegal(MI, Src0Idx, &MI->getOperand(Src1Idx)) ||
!isOperandLegal(MI, Src1Idx, &MI->getOperand(Src0Idx))))
return nullptr;
if (!MI->getOperand(2).isReg()) {
if (Src1Idx != -1 && !MI->getOperand(Src1Idx).isReg()) {
// XXX: Commute instructions with FPImm operands
if (NewMI || MI->getOperand(2).isFPImm() ||
if (NewMI || MI->getOperand(Src1Idx).isFPImm() ||
(!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
return nullptr;
}
@ -716,11 +725,11 @@ MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
(Src2Mods && Src2Mods->getImm()))
return nullptr;
unsigned Reg = MI->getOperand(1).getReg();
unsigned SubReg = MI->getOperand(1).getSubReg();
MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
MI->getOperand(2).ChangeToRegister(Reg, false);
MI->getOperand(2).setSubReg(SubReg);
unsigned Reg = MI->getOperand(Src0Idx).getReg();
unsigned SubReg = MI->getOperand(Src0Idx).getSubReg();
MI->getOperand(Src0Idx).ChangeToImmediate(MI->getOperand(Src1Idx).getImm());
MI->getOperand(Src1Idx).ChangeToRegister(Reg, false);
MI->getOperand(Src1Idx).setSubReg(SubReg);
} else {
MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
}

4
test/CodeGen/R600/llvm.AMDGPU.clamp.ll
View File

@ -6,7 +6,7 @@ declare float @llvm.AMDIL.clamp.f32(float, float, float) nounwind readnone
; FUNC-LABEL: @clamp_0_1_f32
; SI: S_LOAD_DWORD [[ARG:s[0-9]+]],
; SI: V_ADD_F32_e64 [[RESULT:v[0-9]+]], [[ARG]], 0, 1, 0
; SI: V_ADD_F32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]], 1, 0
; SI: BUFFER_STORE_DWORD [[RESULT]]
; SI: S_ENDPGM
@ -19,7 +19,7 @@ define void @clamp_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
; FUNC-LABEL: @clamp_0_1_amdil_legacy_f32
; SI: S_LOAD_DWORD [[ARG:s[0-9]+]],
; SI: V_ADD_F32_e64 [[RESULT:v[0-9]+]], [[ARG]], 0, 1, 0
; SI: V_ADD_F32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]], 1, 0
; SI: BUFFER_STORE_DWORD [[RESULT]]
define void @clamp_0_1_amdil_legacy_f32(float addrspace(1)* %out, float %src) nounwind {
%clamp = call float @llvm.AMDIL.clamp.f32(float %src, float 0.0, float 1.0) nounwind readnone