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[ARM64-BE] Fix fast-isel, and add appropriate RUN lines to appropriate tests.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208200 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
James Molloy 2014-05-07 12:33:55 +00:00
parent d93d214a67
commit 2712c87cfe
4 changed files with 9 additions and 1 deletions
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5
lib/Target/ARM64/ARM64FastISel.cpp
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@ -1593,6 +1593,11 @@ bool ARM64FastISel::SelectRet(const Instruction *I) {
EVT RVEVT = TLI.getValueType(RV->getType());
if (!RVEVT.isSimple())
return false;
// Vectors (of > 1 lane) in big endian need tricky handling.
if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1)
return false;
MVT RVVT = RVEVT.getSimpleVT();
if (RVVT == MVT::f128)
return false;

3
test/CodeGen/ARM64/big-endian-bitconverts.ll
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@ -1,4 +1,5 @@
; RUN: llc -mtriple arm64_be < %s -arm64-load-store-opt=false -o - | FileCheck %s
; RUN: llc -mtriple arm64_be < %s -arm64-load-store-opt=false -O1 -o - | FileCheck %s
; RUN: llc -mtriple arm64_be < %s -arm64-load-store-opt=false -O0 -fast-isel=true -o - | FileCheck %s
; CHECK-LABEL: test_i64_f64:
define void @test_i64_f64(double* %p, i64* %q) {

1
test/CodeGen/ARM64/big-endian-vector-callee.ll
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@ -1,4 +1,5 @@
; RUN: llc -mtriple arm64_be < %s -arm64-load-store-opt=false -o - | FileCheck %s
; RUN: llc -mtriple arm64_be < %s -fast-isel=true -arm64-load-store-opt=false -o - | FileCheck %s
; CHECK-LABEL: test_i64_f64:
define i64 @test_i64_f64(double %p) {

1
test/CodeGen/ARM64/big-endian-vector-caller.ll
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@ -1,4 +1,5 @@
; RUN: llc -mtriple arm64_be < %s -arm64-load-store-opt=false -o - | FileCheck %s
; RUN: llc -mtriple arm64_be < %s -arm64-load-store-opt=false -fast-isel=true -O0 -o - | FileCheck %s
; CHECK-LABEL: test_i64_f64:
declare i64 @test_i64_f64_helper(double %p)