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DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62519 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-01-19 19:06:11 +00:00
parent c1a168a0fc
commit 2722e7b139
2 changed files with 8 additions and 1 deletions
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2
lib/Target/X86/X86ISelDAGToDAG.cpp
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@ -1405,7 +1405,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
InFlag = InFlag =
CurDAG->getCopyToReg(CurDAG->getEntryNode(), CurDAG->getCopyToReg(CurDAG->getEntryNode(),
LoReg, N0, SDValue()).getValue(1); LoReg, N0, SDValue()).getValue(1);
if (isSigned) { if (isSigned && !CurDAG->SignBitIsZero(N0)) {
// Sign extend the low part into the high part. // Sign extend the low part into the high part.
InFlag = InFlag =
SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0); SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);

7
test/CodeGen/X86/rem-2.ll Normal file
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@ -0,0 +1,7 @@
; RUN: llvm-as < %s | llc -march=x86 | not grep cltd
define i32 @test(i32 %X) nounwind readnone {
entry:
%0 = srem i32 41, %X
ret i32 %0
}