6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-09 11:25:55 +00:00
Code Issues Projects Releases Wiki Activity

Fix i64 returns

Browse Source 
Generate PowerPC 'subfic' instruction when appropriate


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20995 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
2005-04-02 00:42:16 +00:00
parent ea19cd51aa
commit 27523a1c92
1 changed files with 9 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
lib/Target/PowerPC/PPCISelPattern.cpp
View File

@@ -488,6 +488,7 @@ static unsigned canUseAsImmediateForOpcode(SDOperand N, unsigned Opcode,
if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; } if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
break; break;
case ISD::MUL: case ISD::MUL:
case ISD::SUB:
if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; } if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
break; break;
case ISD::SETCC: case ISD::SETCC:
@@ -903,10 +904,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
Node->dump(); Node->dump();
assert(0 && "Node not handled!\n"); assert(0 && "Node not handled!\n");
case ISD::UNDEF: case ISD::UNDEF:
if (Result != 1)
ExprMap[N.getValue(1)] = 1;
else
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
BuildMI(BB, PPC::IMPLICIT_DEF, 0, Result); BuildMI(BB, PPC::IMPLICIT_DEF, 0, Result);
return Result; return Result;
case ISD::DYNAMIC_STACKALLOC: case ISD::DYNAMIC_STACKALLOC:
@@ -1212,9 +1209,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
case ISD::SUB: case ISD::SUB:
assert (DestType == MVT::i32 && "Only do arithmetic on i32s!"); assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1)); Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1); if (1 == canUseAsImmediateForOpcode(N.getOperand(0), opcode, Tmp1))
BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp2).addSImm(Tmp1);
else {
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
}
return Result; return Result;
case ISD::MUL: case ISD::MUL:
@@ -1524,8 +1525,8 @@ void ISel::Select(SDOperand N) {
Select(N.getOperand(0)); Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1)); Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = SelectExpr(N.getOperand(2)); Tmp2 = SelectExpr(N.getOperand(2));
BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1); BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp2).addReg(Tmp2);
BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(Tmp2).addReg(Tmp2); BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(Tmp1).addReg(Tmp1);
break; break;
case 2: case 2:
Select(N.getOperand(0)); Select(N.getOperand(0));