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Don't redundantly copy implicit operands when rematerializing.

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While we're at it - don't copy vreg implicit operands while rematerializing.
This fixes PR12138.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151779 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Lang Hames 2012-03-01 00:41:17 +00:00
parent 562a67db32
commit 275ff9bb17
2 changed files with 67 additions and 4 deletions
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13
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -814,7 +814,8 @@ bool RegisterCoalescer::ReMaterializeTrivialDef(LiveInterval &SrcInt,
e = NewMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = NewMI->getOperand(i);
if (MO.isReg()) {
assert(MO.isDef() && MO.isImplicit() && MO.isDead());
assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
NewMIImplDefs.push_back(MO.getReg());
}
}
@ -824,8 +825,13 @@ bool RegisterCoalescer::ReMaterializeTrivialDef(LiveInterval &SrcInt,
for (unsigned i = CopyMI->getDesc().getNumOperands(),
e = CopyMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = CopyMI->getOperand(i);
if (MO.isReg() && MO.isImplicit())
NewMI->addOperand(MO);
if (MO.isReg()) {
assert(MO.isImplicit() && "No explicit operands after implict operands.");
// Discard VReg implicit defs.
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
NewMI->addOperand(MO);
}
}
}
LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
@ -840,7 +846,6 @@ bool RegisterCoalescer::ReMaterializeTrivialDef(LiveInterval &SrcInt,
li.addRange(lr);
}
NewMI->copyImplicitOps(CopyMI);
CopyMI->eraseFromParent();
ReMatCopies.insert(CopyMI);
ReMatDefs.insert(DefMI);

58
test/CodeGen/X86/2012-02-29-CoalescerBug.ll Normal file
View File

@ -0,0 +1,58 @@
; RUN: llc -O1 <%s
; PR12138
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
target triple = "i386-apple-macosx10.7.0"
%struct.S0 = type { i8, i32 }
@d = external global [2 x [2 x %struct.S0]], align 4
@c = external global i32, align 4
@e = external global i32, align 4
@b = external global i32, align 4
@a = external global i32, align 4
define void @fn2() nounwind optsize ssp {
entry:
store i64 0, i64* bitcast ([2 x [2 x %struct.S0]]* @d to i64*), align 4
%0 = load i32* @c, align 4
%tobool2 = icmp eq i32 %0, 0
%1 = load i32* @a, align 4
%tobool4 = icmp eq i32 %1, 0
br label %for.cond
for.cond: ; preds = %if.end, %entry
%f.1.0 = phi i32 [ undef, %entry ], [ %sub, %if.end ]
%g.0 = phi i64 [ 0, %entry ], [ %ins, %if.end ]
%tobool = icmp eq i32 %f.1.0, 0
br i1 %tobool, label %for.end, label %for.body
for.body: ; preds = %for.cond
%2 = lshr i64 %g.0, 32
%conv = trunc i64 %2 to i16
br i1 %tobool2, label %lor.rhs, label %lor.end
lor.rhs: ; preds = %for.body
store i32 1, i32* @e, align 4
br label %lor.end
lor.end: ; preds = %lor.rhs, %for.body
%xor.i = xor i16 %conv, 1
%p1.lobit.i8 = lshr i64 %g.0, 47
%p1.lobit.i8.tr = trunc i64 %p1.lobit.i8 to i16
%p1.lobit.i = and i16 %p1.lobit.i8.tr, 1
%and.i = and i16 %p1.lobit.i, %xor.i
%3 = xor i16 %and.i, 1
%sub.conv.i = sub i16 %conv, %3
%conv3 = sext i16 %sub.conv.i to i32
store i32 %conv3, i32* @b, align 4
br i1 %tobool4, label %if.end, label %for.end
if.end: ; preds = %lor.end
%mask = and i64 %g.0, -256
%ins = or i64 %mask, 1
%sub = add nsw i32 %f.1.0, -1
br label %for.cond
for.end: ; preds = %lor.end, %for.cond
ret void
}