mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-05 13:09:10 +00:00
Teach spiller to unfold instructions which modref spill slot when a scratch
register is available and when it's profitable.
e.g.
xorq %r12<kill>, %r13
addq %rax, -184(%rbp)
addq %r13, -184(%rbp)
==>
xorq %r12<kill>, %r13
movq -184(%rbp), %r12
addq %rax, %r12
addq %r13, %r12
movq %r12, -184(%rbp)
Two more instructions, but fewer memory accesses. It can also open up
opportunities for more optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69341 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
d10a4ce582
commit
276b77e66c
@ -29,6 +29,7 @@ STATISTIC(NumLoads , "Number of loads added");
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STATISTIC(NumReused , "Number of values reused");
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STATISTIC(NumDCE , "Number of copies elided");
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STATISTIC(NumSUnfold , "Number of stores unfolded");
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STATISTIC(NumModRefUnfold, "Number of modref unfolded");
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namespace {
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enum SpillerName { simple, local };
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@ -524,6 +525,7 @@ bool LocalSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
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RegInfo = &MF.getRegInfo();
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TRI = MF.getTarget().getRegisterInfo();
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TII = MF.getTarget().getInstrInfo();
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AllocatableRegs = TRI->getAllocatableSet(MF);
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DOUT << "\n**** Local spiller rewriting function '"
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<< MF.getFunction()->getName() << "':\n";
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DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)"
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@ -595,7 +597,201 @@ bool LocalSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
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}
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/// PrepForUnfoldOpti - Turn a store folding instruction into a load folding
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/// FoldsStackSlotModRef - Return true if the specified MI folds the specified
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/// stack slot mod/ref. It also checks if it's possible to unfold the
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/// instruction by having it define a specified physical register instead.
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static bool FoldsStackSlotModRef(MachineInstr &MI, int SS, unsigned PhysReg,
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const TargetInstrInfo *TII,
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const TargetRegisterInfo *TRI,
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VirtRegMap &VRM) {
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if (VRM.hasEmergencySpills(&MI) || VRM.isSpillPt(&MI))
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return false;
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bool Found = false;
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VirtRegMap::MI2VirtMapTy::const_iterator I, End;
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for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
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unsigned VirtReg = I->second.first;
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VirtRegMap::ModRef MR = I->second.second;
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if (MR & VirtRegMap::isModRef)
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if (VRM.getStackSlot(VirtReg) == SS) {
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Found= TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), true, true) != 0;
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break;
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}
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}
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if (!Found)
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return false;
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// Does the instruction uses a register that overlaps the scratch register?
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI.getOperand(i);
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if (!MO.isReg() || MO.getReg() == 0)
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continue;
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unsigned Reg = MO.getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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if (!VRM.hasPhys(Reg))
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continue;
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Reg = VRM.getPhys(Reg);
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}
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if (TRI->regsOverlap(PhysReg, Reg))
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return false;
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}
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return true;
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}
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/// FindFreeRegister - Find a free register of a given register class by looking
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/// at (at most) the last two machine instructions.
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static unsigned FindFreeRegister(MachineBasicBlock::iterator MII,
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MachineBasicBlock &MBB,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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BitVector &AllocatableRegs) {
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BitVector Defs(TRI->getNumRegs());
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BitVector Uses(TRI->getNumRegs());
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SmallVector<unsigned, 4> LocalUses;
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SmallVector<unsigned, 4> Kills;
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// Take a look at 2 instructions at most.
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for (unsigned Count = 0; Count < 2; ++Count) {
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if (MII == MBB.begin())
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break;
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MachineInstr *PrevMI = prior(MII);
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for (unsigned i = 0, e = PrevMI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = PrevMI->getOperand(i);
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if (!MO.isReg() || MO.getReg() == 0)
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continue;
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unsigned Reg = MO.getReg();
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if (MO.isDef()) {
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Defs.set(Reg);
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
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Defs.set(*AS);
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} else {
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LocalUses.push_back(Reg);
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if (MO.isKill() && AllocatableRegs[Reg])
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Kills.push_back(Reg);
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}
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}
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for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
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unsigned Kill = Kills[i];
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if (!Defs[Kill] && !Uses[Kill] &&
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TRI->getPhysicalRegisterRegClass(Kill) == RC)
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return Kill;
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}
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for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
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unsigned Reg = LocalUses[i];
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Uses.set(Reg);
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
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Uses.set(*AS);
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}
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MII = PrevMI;
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}
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return 0;
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}
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static
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void AssignPhysToVirtReg(MachineInstr *MI, unsigned VirtReg, unsigned PhysReg) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.getReg() == VirtReg)
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MO.setReg(PhysReg);
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}
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}
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/// OptimizeByUnfold2 - Unfold a series of load / store folding instructions if
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/// a scratch register is available.
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/// xorq %r12<kill>, %r13
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/// addq %rax, -184(%rbp)
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/// addq %r13, -184(%rbp)
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/// ==>
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/// xorq %r12<kill>, %r13
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/// movq -184(%rbp), %r12
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/// addq %rax, %r12
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/// addq %r13, %r12
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/// movq %r12, -184(%rbp)
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bool LocalSpiller::OptimizeByUnfold2(unsigned VirtReg, int SS,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MII,
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std::vector<MachineInstr*> &MaybeDeadStores,
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AvailableSpills &Spills,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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VirtRegMap &VRM) {
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MachineBasicBlock::iterator NextMII = next(MII);
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if (NextMII == MBB.end())
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return false;
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if (TII->getOpcodeAfterMemoryUnfold(MII->getOpcode(), true, true) == 0)
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return false;
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// Now let's see if the last couple of instructions happens to have freed up
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// a register.
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const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
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unsigned PhysReg = FindFreeRegister(MII, MBB, RC, TRI, AllocatableRegs);
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if (!PhysReg)
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return false;
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MachineFunction &MF = *MBB.getParent();
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TRI = MF.getTarget().getRegisterInfo();
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MachineInstr &MI = *MII;
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if (!FoldsStackSlotModRef(MI, SS, PhysReg, TII, TRI, VRM))
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return false;
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// If the next instruction also folds the same SS modref and can be unfoled,
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// then it's worthwhile to issue a load from SS into the free register and
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// then unfold these instructions.
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if (!FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, VRM))
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return false;
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// Load from SS to the spare physical register.
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TII->loadRegFromStackSlot(MBB, MII, PhysReg, SS, RC);
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// This invalidates Phys.
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Spills.ClobberPhysReg(PhysReg);
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// Remember it's available.
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Spills.addAvailable(SS, PhysReg);
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MaybeDeadStores[SS] = NULL;
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// Unfold current MI.
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SmallVector<MachineInstr*, 4> NewMIs;
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if (!TII->unfoldMemoryOperand(MF, &MI, VirtReg, false, false, NewMIs))
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assert(0 && "Unable unfold the load / store folding instruction!");
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assert(NewMIs.size() == 1);
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AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg);
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VRM.transferRestorePts(&MI, NewMIs[0]);
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MII = MBB.insert(MII, NewMIs[0]);
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InvalidateKills(MI, RegKills, KillOps);
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VRM.RemoveMachineInstrFromMaps(&MI);
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MBB.erase(&MI);
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++NumModRefUnfold;
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// Unfold next instructions that fold the same SS.
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do {
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MachineInstr &NextMI = *NextMII;
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NextMII = next(NextMII);
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NewMIs.clear();
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if (!TII->unfoldMemoryOperand(MF, &NextMI, VirtReg, false, false, NewMIs))
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assert(0 && "Unable unfold the load / store folding instruction!");
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assert(NewMIs.size() == 1);
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AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg);
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VRM.transferRestorePts(&NextMI, NewMIs[0]);
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MBB.insert(NextMII, NewMIs[0]);
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InvalidateKills(NextMI, RegKills, KillOps);
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VRM.RemoveMachineInstrFromMaps(&NextMI);
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MBB.erase(&NextMI);
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++NumModRefUnfold;
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} while (FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, VRM));
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// Store the value back into SS.
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TII->storeRegToStackSlot(MBB, NextMII, PhysReg, true, SS, RC);
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MachineInstr *StoreMI = prior(NextMII);
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VRM.addSpillSlotUse(SS, StoreMI);
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VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
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return true;
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}
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/// OptimizeByUnfold - Turn a store folding instruction into a load folding
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/// instruction. e.g.
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/// xorl %edi, %eax
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/// movl %eax, -32(%ebp)
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@ -607,7 +803,7 @@ bool LocalSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
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/// mov %eax, -32(%ebp)
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/// This enables unfolding optimization for a subsequent instruction which will
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/// also eliminate the newly introduced store instruction.
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bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
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bool LocalSpiller::OptimizeByUnfold(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MII,
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std::vector<MachineInstr*> &MaybeDeadStores,
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AvailableSpills &Spills,
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@ -646,8 +842,14 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
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}
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}
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if (!UnfoldedOpc)
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return false;
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if (!UnfoldedOpc) {
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if (!UnfoldVR)
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return false;
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// Look for other unfolding opportunities.
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return OptimizeByUnfold2(UnfoldVR, FoldedSS, MBB, MII,
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MaybeDeadStores, Spills, RegKills, KillOps, VRM);
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}
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI.getOperand(i);
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@ -705,6 +907,7 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
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MF.DeleteMachineInstr(NewMI);
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}
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}
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return false;
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}
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@ -770,7 +973,7 @@ bool LocalSpiller::CommuteToFoldReload(MachineBasicBlock &MBB,
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VRM.addSpillSlotUse(SS, FoldedMI);
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VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
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// Insert new def MI and spill MI.
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const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg);
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const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
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TII->storeRegToStackSlot(MBB, &MI, NewReg, true, SS, RC);
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MII = prior(MII);
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MachineInstr *StoreMI = MII;
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@ -935,13 +1138,13 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
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DistanceMap.clear();
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for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
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MII != E; ) {
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MachineBasicBlock::iterator NextMII = MII; ++NextMII;
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MachineBasicBlock::iterator NextMII = next(MII);
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VirtRegMap::MI2VirtMapTy::const_iterator I, End;
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bool Erased = false;
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bool BackTracked = false;
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if (PrepForUnfoldOpti(MBB, MII,
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MaybeDeadStores, Spills, RegKills, KillOps, VRM))
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if (OptimizeByUnfold(MBB, MII,
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MaybeDeadStores, Spills, RegKills, KillOps, VRM))
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NextMII = next(MII);
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MachineInstr &MI = *MII;
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@ -97,7 +97,7 @@ namespace llvm {
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const TargetRegisterInfo *getRegInfo() const { return TRI; }
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/// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
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/// available in a physical register, return that PhysReg, otherwise
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/// available in a physical register, return that PhysReg, otherwise
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/// return 0.
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unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
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std::map<int, unsigned>::const_iterator I =
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@ -284,6 +284,7 @@ namespace llvm {
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MachineRegisterInfo *RegInfo;
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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BitVector AllocatableRegs;
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DenseMap<MachineInstr*, unsigned> DistanceMap;
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public:
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bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM);
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@ -291,12 +292,22 @@ namespace llvm {
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void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist,
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unsigned Reg, BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps);
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bool PrepForUnfoldOpti(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MII,
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bool OptimizeByUnfold(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MII,
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std::vector<MachineInstr*> &MaybeDeadStores,
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AvailableSpills &Spills, BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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VirtRegMap &VRM);
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bool OptimizeByUnfold2(unsigned VirtReg, int SS,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MII,
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std::vector<MachineInstr*> &MaybeDeadStores,
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AvailableSpills &Spills, BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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VirtRegMap &VRM);
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bool CommuteToFoldReload(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MII,
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unsigned VirtReg, unsigned SrcReg, int SS,
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@ -305,6 +316,7 @@ namespace llvm {
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std::vector<MachineOperand*> &KillOps,
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const TargetRegisterInfo *TRI,
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VirtRegMap &VRM);
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void SpillRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MII,
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int Idx, unsigned PhysReg, int StackSlot,
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@ -315,6 +327,7 @@ namespace llvm {
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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VirtRegMap &VRM);
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void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
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AvailableSpills &Spills,
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BitVector &RegKills, std::vector<MachineOperand*> &KillOps);
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139
test/CodeGen/X86/2009-04-16-SpillerUnfold.ll
Normal file
139
test/CodeGen/X86/2009-04-16-SpillerUnfold.ll
Normal file
@ -0,0 +1,139 @@
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; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of modref unfolded}
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%struct.SHA512_CTX = type { [8 x i64], i64, i64, %struct.anon, i32, i32 }
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%struct.anon = type { [16 x i64] }
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@K512 = external constant [80 x i64], align 32 ; <[80 x i64]*> [#uses=2]
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define fastcc void @sha512_block_data_order(%struct.SHA512_CTX* nocapture %ctx, i8* nocapture %in, i64 %num) nounwind ssp {
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entry:
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br label %bb349
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bb349: ; preds = %bb349, %entry
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%e.0489 = phi i64 [ 0, %entry ], [ %e.0, %bb349 ] ; <i64> [#uses=3]
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%b.0472 = phi i64 [ 0, %entry ], [ %87, %bb349 ] ; <i64> [#uses=2]
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%asmtmp356 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 41, i64 %e.0489) nounwind ; <i64> [#uses=1]
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%0 = xor i64 0, %asmtmp356 ; <i64> [#uses=1]
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%1 = add i64 0, %0 ; <i64> [#uses=1]
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%2 = add i64 %1, 0 ; <i64> [#uses=1]
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%3 = add i64 %2, 0 ; <i64> [#uses=1]
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%4 = add i64 %3, 0 ; <i64> [#uses=5]
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%asmtmp372 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 34, i64 %4) nounwind ; <i64> [#uses=1]
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%asmtmp373 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 39, i64 %4) nounwind ; <i64> [#uses=0]
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%5 = xor i64 %asmtmp372, 0 ; <i64> [#uses=0]
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%6 = xor i64 0, %b.0472 ; <i64> [#uses=1]
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%7 = and i64 %4, %6 ; <i64> [#uses=1]
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%8 = xor i64 %7, 0 ; <i64> [#uses=1]
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%9 = add i64 0, %8 ; <i64> [#uses=1]
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%10 = add i64 %9, 0 ; <i64> [#uses=2]
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%asmtmp377 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 61, i64 0) nounwind ; <i64> [#uses=1]
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%11 = xor i64 0, %asmtmp377 ; <i64> [#uses=1]
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%12 = add i64 0, %11 ; <i64> [#uses=1]
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%13 = add i64 %12, 0 ; <i64> [#uses=1]
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%not381 = xor i64 0, -1 ; <i64> [#uses=1]
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%14 = and i64 %e.0489, %not381 ; <i64> [#uses=1]
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%15 = xor i64 0, %14 ; <i64> [#uses=1]
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%16 = add i64 %15, 0 ; <i64> [#uses=1]
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%17 = add i64 %16, %13 ; <i64> [#uses=1]
|
||||
%18 = add i64 %17, 0 ; <i64> [#uses=1]
|
||||
%19 = add i64 %18, 0 ; <i64> [#uses=2]
|
||||
%20 = add i64 %19, %b.0472 ; <i64> [#uses=3]
|
||||
%21 = add i64 %19, 0 ; <i64> [#uses=1]
|
||||
%22 = add i64 %21, 0 ; <i64> [#uses=1]
|
||||
%23 = add i32 0, 12 ; <i32> [#uses=1]
|
||||
%24 = and i32 %23, 12 ; <i32> [#uses=1]
|
||||
%25 = zext i32 %24 to i64 ; <i64> [#uses=1]
|
||||
%26 = getelementptr [16 x i64]* null, i64 0, i64 %25 ; <i64*> [#uses=0]
|
||||
%27 = add i64 0, %e.0489 ; <i64> [#uses=1]
|
||||
%28 = add i64 %27, 0 ; <i64> [#uses=1]
|
||||
%29 = add i64 %28, 0 ; <i64> [#uses=1]
|
||||
%30 = add i64 %29, 0 ; <i64> [#uses=2]
|
||||
%31 = and i64 %10, %4 ; <i64> [#uses=1]
|
||||
%32 = xor i64 0, %31 ; <i64> [#uses=1]
|
||||
%33 = add i64 %30, 0 ; <i64> [#uses=3]
|
||||
%34 = add i64 %30, %32 ; <i64> [#uses=1]
|
||||
%35 = add i64 %34, 0 ; <i64> [#uses=1]
|
||||
%36 = and i64 %33, %20 ; <i64> [#uses=1]
|
||||
%37 = xor i64 %36, 0 ; <i64> [#uses=1]
|
||||
%38 = add i64 %37, 0 ; <i64> [#uses=1]
|
||||
%39 = add i64 %38, 0 ; <i64> [#uses=1]
|
||||
%40 = add i64 %39, 0 ; <i64> [#uses=1]
|
||||
%41 = add i64 %40, 0 ; <i64> [#uses=1]
|
||||
%42 = add i64 %41, %4 ; <i64> [#uses=3]
|
||||
%43 = or i32 0, 6 ; <i32> [#uses=1]
|
||||
%44 = and i32 %43, 14 ; <i32> [#uses=1]
|
||||
%45 = zext i32 %44 to i64 ; <i64> [#uses=1]
|
||||
%46 = getelementptr [16 x i64]* null, i64 0, i64 %45 ; <i64*> [#uses=1]
|
||||
%not417 = xor i64 %42, -1 ; <i64> [#uses=1]
|
||||
%47 = and i64 %20, %not417 ; <i64> [#uses=1]
|
||||
%48 = xor i64 0, %47 ; <i64> [#uses=1]
|
||||
%49 = getelementptr [80 x i64]* @K512, i64 0, i64 0 ; <i64*> [#uses=1]
|
||||
%50 = load i64* %49, align 8 ; <i64> [#uses=1]
|
||||
%51 = add i64 %48, 0 ; <i64> [#uses=1]
|
||||
%52 = add i64 %51, 0 ; <i64> [#uses=1]
|
||||
%53 = add i64 %52, 0 ; <i64> [#uses=1]
|
||||
%54 = add i64 %53, %50 ; <i64> [#uses=2]
|
||||
%asmtmp420 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 34, i64 0) nounwind ; <i64> [#uses=1]
|
||||
%asmtmp421 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 39, i64 0) nounwind ; <i64> [#uses=1]
|
||||
%55 = xor i64 %asmtmp420, 0 ; <i64> [#uses=1]
|
||||
%56 = xor i64 %55, %asmtmp421 ; <i64> [#uses=1]
|
||||
%57 = add i64 %54, %10 ; <i64> [#uses=5]
|
||||
%58 = add i64 %54, 0 ; <i64> [#uses=1]
|
||||
%59 = add i64 %58, %56 ; <i64> [#uses=2]
|
||||
%60 = or i32 0, 7 ; <i32> [#uses=1]
|
||||
%61 = and i32 %60, 15 ; <i32> [#uses=1]
|
||||
%62 = zext i32 %61 to i64 ; <i64> [#uses=1]
|
||||
%63 = getelementptr [16 x i64]* null, i64 0, i64 %62 ; <i64*> [#uses=2]
|
||||
%64 = load i64* null, align 8 ; <i64> [#uses=1]
|
||||
%65 = lshr i64 %64, 6 ; <i64> [#uses=1]
|
||||
%66 = xor i64 0, %65 ; <i64> [#uses=1]
|
||||
%67 = xor i64 %66, 0 ; <i64> [#uses=1]
|
||||
%68 = load i64* %46, align 8 ; <i64> [#uses=1]
|
||||
%69 = load i64* null, align 8 ; <i64> [#uses=1]
|
||||
%70 = add i64 %68, 0 ; <i64> [#uses=1]
|
||||
%71 = add i64 %70, %67 ; <i64> [#uses=1]
|
||||
%72 = add i64 %71, %69 ; <i64> [#uses=1]
|
||||
%asmtmp427 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 18, i64 %57) nounwind ; <i64> [#uses=1]
|
||||
%asmtmp428 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 41, i64 %57) nounwind ; <i64> [#uses=1]
|
||||
%73 = xor i64 %asmtmp427, 0 ; <i64> [#uses=1]
|
||||
%74 = xor i64 %73, %asmtmp428 ; <i64> [#uses=1]
|
||||
%75 = and i64 %57, %42 ; <i64> [#uses=1]
|
||||
%not429 = xor i64 %57, -1 ; <i64> [#uses=1]
|
||||
%76 = and i64 %33, %not429 ; <i64> [#uses=1]
|
||||
%77 = xor i64 %75, %76 ; <i64> [#uses=1]
|
||||
%78 = getelementptr [80 x i64]* @K512, i64 0, i64 0 ; <i64*> [#uses=1]
|
||||
%79 = load i64* %78, align 16 ; <i64> [#uses=1]
|
||||
%80 = add i64 %77, %20 ; <i64> [#uses=1]
|
||||
%81 = add i64 %80, %72 ; <i64> [#uses=1]
|
||||
%82 = add i64 %81, %74 ; <i64> [#uses=1]
|
||||
%83 = add i64 %82, %79 ; <i64> [#uses=1]
|
||||
%asmtmp432 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 34, i64 %59) nounwind ; <i64> [#uses=1]
|
||||
%asmtmp433 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 39, i64 %59) nounwind ; <i64> [#uses=1]
|
||||
%84 = xor i64 %asmtmp432, 0 ; <i64> [#uses=1]
|
||||
%85 = xor i64 %84, %asmtmp433 ; <i64> [#uses=1]
|
||||
%86 = add i64 %83, %22 ; <i64> [#uses=2]
|
||||
%87 = add i64 0, %85 ; <i64> [#uses=1]
|
||||
%asmtmp435 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 8, i64 0) nounwind ; <i64> [#uses=1]
|
||||
%88 = xor i64 0, %asmtmp435 ; <i64> [#uses=1]
|
||||
%89 = load i64* null, align 8 ; <i64> [#uses=3]
|
||||
%asmtmp436 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 19, i64 %89) nounwind ; <i64> [#uses=1]
|
||||
%asmtmp437 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 61, i64 %89) nounwind ; <i64> [#uses=1]
|
||||
%90 = lshr i64 %89, 6 ; <i64> [#uses=1]
|
||||
%91 = xor i64 %asmtmp436, %90 ; <i64> [#uses=1]
|
||||
%92 = xor i64 %91, %asmtmp437 ; <i64> [#uses=1]
|
||||
%93 = load i64* %63, align 8 ; <i64> [#uses=1]
|
||||
%94 = load i64* null, align 8 ; <i64> [#uses=1]
|
||||
%95 = add i64 %93, %88 ; <i64> [#uses=1]
|
||||
%96 = add i64 %95, %92 ; <i64> [#uses=1]
|
||||
%97 = add i64 %96, %94 ; <i64> [#uses=2]
|
||||
store i64 %97, i64* %63, align 8
|
||||
%98 = and i64 %86, %57 ; <i64> [#uses=1]
|
||||
%not441 = xor i64 %86, -1 ; <i64> [#uses=1]
|
||||
%99 = and i64 %42, %not441 ; <i64> [#uses=1]
|
||||
%100 = xor i64 %98, %99 ; <i64> [#uses=1]
|
||||
%101 = add i64 %100, %33 ; <i64> [#uses=1]
|
||||
%102 = add i64 %101, %97 ; <i64> [#uses=1]
|
||||
%103 = add i64 %102, 0 ; <i64> [#uses=1]
|
||||
%104 = add i64 %103, 0 ; <i64> [#uses=1]
|
||||
%e.0 = add i64 %104, %35 ; <i64> [#uses=1]
|
||||
br label %bb349
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user