Clean up some style and formatting issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213418 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2014-07-18 22:34:14 +00:00
parent d2e8729d1d
commit 277c0d6254

View File

@ -44,9 +44,8 @@ const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
/// the destination along with the FrameIndex of the loaded stack slot. If /// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has /// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot. /// any side effects other than loading from the stack slot.
unsigned Mips16InstrInfo:: unsigned Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const int &FrameIndex) const {
{
return 0; return 0;
} }
@ -55,9 +54,8 @@ isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
/// the source reg along with the FrameIndex of the loaded stack slot. If /// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has /// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot. /// any side effects other than storing to the stack slot.
unsigned Mips16InstrInfo:: unsigned Mips16InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const int &FrameIndex) const {
{
return 0; return 0;
} }
@ -93,10 +91,11 @@ void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MIB.addReg(SrcReg, getKillRegState(KillSrc)); MIB.addReg(SrcReg, getKillRegState(KillSrc));
} }
void Mips16InstrInfo:: void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,
storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI, unsigned SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
int64_t Offset) const { int64_t Offset) const {
DebugLoc DL; DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc(); if (I != MBB.end()) DL = I->getDebugLoc();
@ -110,10 +109,12 @@ storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
.addMemOperand(MMO); .addMemOperand(MMO);
} }
void Mips16InstrInfo:: void Mips16InstrInfo::loadRegFromStack(MachineBasicBlock &MBB,
loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned DestReg, int FI, const TargetRegisterClass *RC, unsigned DestReg, int FI,
const TargetRegisterInfo *TRI, int64_t Offset) const { const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
int64_t Offset) const {
DebugLoc DL; DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc(); if (I != MBB.end()) DL = I->getDebugLoc();
MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
@ -171,7 +172,8 @@ unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
} }
static void addSaveRestoreRegs(MachineInstrBuilder &MIB, static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
const std::vector<CalleeSavedInfo> &CSI, unsigned Flags=0) { const std::vector<CalleeSavedInfo> &CSI,
unsigned Flags = 0) {
for (unsigned i = 0, e = CSI.size(); i != e; ++i) { for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
// Add the callee-saved register as live-in. Do not add if the register is // Add the callee-saved register as live-in. Do not add if the register is
// RA and return address is taken, because it has already been added in // RA and return address is taken, because it has already been added in
@ -287,8 +289,8 @@ void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
MIB4.addReg(Reg1, RegState::Kill); MIB4.addReg(Reg1, RegState::Kill);
} }
void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount, void Mips16InstrInfo::adjustStackPtrBigUnrestricted(
MachineBasicBlock &MBB, unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const { MachineBasicBlock::iterator I) const {
assert(false && "adjust stack pointer amount exceeded"); assert(false && "adjust stack pointer amount exceeded");
} }
@ -305,11 +307,10 @@ void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
/// This function generates the sequence of instructions needed to get the /// This function generates the sequence of instructions needed to get the
/// result of adding register REG and immediate IMM. /// result of adding register REG and immediate IMM.
unsigned unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
Mips16InstrInfo::loadImmediate(unsigned FrameReg, MachineBasicBlock &MBB,
int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II,
MachineBasicBlock::iterator II, DebugLoc DL, DebugLoc DL, unsigned &NewImm) const {
unsigned &NewImm) const {
// //
// given original instruction is: // given original instruction is:
// Instr rx, T[offset] where offset is too big. // Instr rx, T[offset] where offset is too big.
@ -345,7 +346,7 @@ Mips16InstrInfo::loadImmediate(unsigned FrameReg,
!TargetRegisterInfo::isVirtualRegister(MO.getReg())) !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
Candidates.reset(MO.getReg()); Candidates.reset(MO.getReg());
} }
//
// If the same register was used and defined in an instruction, then // If the same register was used and defined in an instruction, then
// it will not be in the list of candidates. // it will not be in the list of candidates.
// //
@ -354,7 +355,6 @@ Mips16InstrInfo::loadImmediate(unsigned FrameReg,
// present as an operand of the instruction. this tells // present as an operand of the instruction. this tells
// whether the register is live before the instruction. if it's not // whether the register is live before the instruction. if it's not
// then we don't need to save it in case there are no free registers. // then we don't need to save it in case there are no free registers.
//
int DefReg = 0; int DefReg = 0;
for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
MachineOperand &MO = II->getOperand(i); MachineOperand &MO = II->getOperand(i);
@ -363,9 +363,8 @@ Mips16InstrInfo::loadImmediate(unsigned FrameReg,
break; break;
} }
} }
//
BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
Available &= Candidates; Available &= Candidates;
// //
// we use T0 for the first register, if we need to save something away. // we use T0 for the first register, if we need to save something away.
@ -374,7 +373,6 @@ Mips16InstrInfo::loadImmediate(unsigned FrameReg,
unsigned FirstRegSaved =0, SecondRegSaved=0; unsigned FirstRegSaved =0, SecondRegSaved=0;
unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0; unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
Reg = Available.find_first(); Reg = Available.find_first();
if (Reg == -1) { if (Reg == -1) {
@ -442,7 +440,6 @@ void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
} }
const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const { const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
if (validSpImm8(Imm)) if (validSpImm8(Imm))
return get(Mips::AddiuSpImm16); return get(Mips::AddiuSpImm16);
@ -497,7 +494,6 @@ bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str, unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str,
const MCAsmInfo &MAI) const { const MCAsmInfo &MAI) const {
// Count the number of instructions in the asm. // Count the number of instructions in the asm.
bool atInsnStart = true; bool atInsnStart = true;
unsigned Length = 0; unsigned Length = 0;