mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 07:11:49 +00:00
Add XOP disassembler support. Fixes PR13933.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191874 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
dfd1014ec3
commit
279d28265d
@ -81,6 +81,15 @@ static int modRMRequired(OpcodeType type,
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case THREEBYTE_A7:
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decision = &THREEBYTEA7_SYM;
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break;
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case XOP8_MAP:
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decision = &XOP8_MAP_SYM;
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break;
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case XOP9_MAP:
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decision = &XOP9_MAP_SYM;
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break;
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case XOPA_MAP:
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decision = &XOPA_MAP_SYM;
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break;
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}
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return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
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@ -122,6 +131,15 @@ static InstrUID decode(OpcodeType type,
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case THREEBYTE_A7:
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dec = &THREEBYTEA7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
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break;
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case XOP8_MAP:
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dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
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break;
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case XOP9_MAP:
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dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
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break;
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case XOPA_MAP:
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dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
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break;
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}
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switch (dec->modrm_type) {
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@ -428,7 +446,7 @@ static int readPrefixes(struct InternalInstruction* insn) {
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dbgprintf(insn, "Found prefix 0x%hhx", byte);
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}
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insn->vexSize = 0;
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insn->vexXopType = TYPE_NO_VEX_XOP;
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if (byte == 0xc4) {
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uint8_t byte1;
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@ -439,7 +457,7 @@ static int readPrefixes(struct InternalInstruction* insn) {
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}
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if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
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insn->vexSize = 3;
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insn->vexXopType = TYPE_VEX_3B;
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insn->necessaryPrefixLocation = insn->readerCursor - 1;
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}
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else {
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@ -447,22 +465,22 @@ static int readPrefixes(struct InternalInstruction* insn) {
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insn->necessaryPrefixLocation = insn->readerCursor - 1;
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}
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if (insn->vexSize == 3) {
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insn->vexPrefix[0] = byte;
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consumeByte(insn, &insn->vexPrefix[1]);
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consumeByte(insn, &insn->vexPrefix[2]);
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if (insn->vexXopType == TYPE_VEX_3B) {
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insn->vexXopPrefix[0] = byte;
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consumeByte(insn, &insn->vexXopPrefix[1]);
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consumeByte(insn, &insn->vexXopPrefix[2]);
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/* We simulate the REX prefix for simplicity's sake */
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if (insn->mode == MODE_64BIT) {
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insn->rexPrefix = 0x40
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| (wFromVEX3of3(insn->vexPrefix[2]) << 3)
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| (rFromVEX2of3(insn->vexPrefix[1]) << 2)
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| (xFromVEX2of3(insn->vexPrefix[1]) << 1)
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| (bFromVEX2of3(insn->vexPrefix[1]) << 0);
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| (wFromVEX3of3(insn->vexXopPrefix[2]) << 3)
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| (rFromVEX2of3(insn->vexXopPrefix[1]) << 2)
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| (xFromVEX2of3(insn->vexXopPrefix[1]) << 1)
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| (bFromVEX2of3(insn->vexXopPrefix[1]) << 0);
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}
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switch (ppFromVEX3of3(insn->vexPrefix[2]))
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switch (ppFromVEX3of3(insn->vexXopPrefix[2]))
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{
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default:
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break;
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@ -471,7 +489,9 @@ static int readPrefixes(struct InternalInstruction* insn) {
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break;
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}
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dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx", insn->vexPrefix[0], insn->vexPrefix[1], insn->vexPrefix[2]);
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dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
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insn->vexXopPrefix[0], insn->vexXopPrefix[1],
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insn->vexXopPrefix[2]);
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}
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}
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else if (byte == 0xc5) {
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@ -483,22 +503,22 @@ static int readPrefixes(struct InternalInstruction* insn) {
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}
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if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
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insn->vexSize = 2;
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insn->vexXopType = TYPE_VEX_2B;
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}
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else {
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unconsumeByte(insn);
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}
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if (insn->vexSize == 2) {
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insn->vexPrefix[0] = byte;
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consumeByte(insn, &insn->vexPrefix[1]);
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if (insn->vexXopType == TYPE_VEX_2B) {
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insn->vexXopPrefix[0] = byte;
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consumeByte(insn, &insn->vexXopPrefix[1]);
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if (insn->mode == MODE_64BIT) {
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insn->rexPrefix = 0x40
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| (rFromVEX2of2(insn->vexPrefix[1]) << 2);
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| (rFromVEX2of2(insn->vexXopPrefix[1]) << 2);
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}
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switch (ppFromVEX2of2(insn->vexPrefix[1]))
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switch (ppFromVEX2of2(insn->vexXopPrefix[1]))
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{
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default:
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break;
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@ -507,7 +527,53 @@ static int readPrefixes(struct InternalInstruction* insn) {
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break;
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}
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dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx", insn->vexPrefix[0], insn->vexPrefix[1]);
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dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx", insn->vexXopPrefix[0], insn->vexXopPrefix[1]);
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}
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}
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else if (byte == 0x8f) {
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uint8_t byte1;
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if (lookAtByte(insn, &byte1)) {
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dbgprintf(insn, "Couldn't read second byte of XOP");
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return -1;
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}
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if ((byte1 & 0x38) != 0x0) { // 0 in these 3 bits is a POP instruction.
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insn->vexXopType = TYPE_XOP;
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insn->necessaryPrefixLocation = insn->readerCursor - 1;
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}
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else {
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unconsumeByte(insn);
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insn->necessaryPrefixLocation = insn->readerCursor - 1;
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}
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if (insn->vexXopType == TYPE_XOP) {
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insn->vexXopPrefix[0] = byte;
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consumeByte(insn, &insn->vexXopPrefix[1]);
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consumeByte(insn, &insn->vexXopPrefix[2]);
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/* We simulate the REX prefix for simplicity's sake */
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if (insn->mode == MODE_64BIT) {
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insn->rexPrefix = 0x40
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| (wFromXOP3of3(insn->vexXopPrefix[2]) << 3)
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| (rFromXOP2of3(insn->vexXopPrefix[1]) << 2)
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| (xFromXOP2of3(insn->vexXopPrefix[1]) << 1)
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| (bFromXOP2of3(insn->vexXopPrefix[1]) << 0);
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}
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switch (ppFromXOP3of3(insn->vexXopPrefix[2]))
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{
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default:
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break;
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case VEX_PREFIX_66:
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hasOpSize = TRUE;
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break;
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}
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dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
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insn->vexXopPrefix[0], insn->vexXopPrefix[1],
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insn->vexXopPrefix[2]);
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}
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}
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else {
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@ -582,12 +648,13 @@ static int readOpcode(struct InternalInstruction* insn) {
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insn->opcodeType = ONEBYTE;
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if (insn->vexSize == 3)
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if (insn->vexXopType == TYPE_VEX_3B)
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{
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switch (mmmmmFromVEX2of3(insn->vexPrefix[1]))
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switch (mmmmmFromVEX2of3(insn->vexXopPrefix[1]))
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{
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default:
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dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", mmmmmFromVEX2of3(insn->vexPrefix[1]));
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dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
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mmmmmFromVEX2of3(insn->vexXopPrefix[1]));
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return -1;
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case VEX_LOB_0F:
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insn->opcodeType = TWOBYTE;
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@ -600,11 +667,30 @@ static int readOpcode(struct InternalInstruction* insn) {
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return consumeByte(insn, &insn->opcode);
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}
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}
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else if (insn->vexSize == 2)
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else if (insn->vexXopType == TYPE_VEX_2B)
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{
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insn->opcodeType = TWOBYTE;
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return consumeByte(insn, &insn->opcode);
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}
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else if (insn->vexXopType == TYPE_XOP)
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{
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switch (mmmmmFromXOP2of3(insn->vexXopPrefix[1]))
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{
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default:
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dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
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mmmmmFromVEX2of3(insn->vexXopPrefix[1]));
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return -1;
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case XOP_MAP_SELECT_8:
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insn->opcodeType = XOP8_MAP;
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return consumeByte(insn, &insn->opcode);
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case XOP_MAP_SELECT_9:
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insn->opcodeType = XOP9_MAP;
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return consumeByte(insn, &insn->opcode);
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case XOP_MAP_SELECT_A:
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insn->opcodeType = XOPA_MAP;
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return consumeByte(insn, &insn->opcode);
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}
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}
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if (consumeByte(insn, ¤t))
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return -1;
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@ -752,11 +838,11 @@ static int getID(struct InternalInstruction* insn, const void *miiArg) {
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if (insn->mode == MODE_64BIT)
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attrMask |= ATTR_64BIT;
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if (insn->vexSize) {
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if (insn->vexXopType != TYPE_NO_VEX_XOP) {
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attrMask |= ATTR_VEX;
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if (insn->vexSize == 3) {
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switch (ppFromVEX3of3(insn->vexPrefix[2])) {
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if (insn->vexXopType == TYPE_VEX_3B) {
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switch (ppFromVEX3of3(insn->vexXopPrefix[2])) {
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case VEX_PREFIX_66:
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attrMask |= ATTR_OPSIZE;
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break;
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@ -768,11 +854,11 @@ static int getID(struct InternalInstruction* insn, const void *miiArg) {
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break;
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}
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if (lFromVEX3of3(insn->vexPrefix[2]))
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if (lFromVEX3of3(insn->vexXopPrefix[2]))
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attrMask |= ATTR_VEXL;
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}
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else if (insn->vexSize == 2) {
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switch (ppFromVEX2of2(insn->vexPrefix[1])) {
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else if (insn->vexXopType == TYPE_VEX_2B) {
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switch (ppFromVEX2of2(insn->vexXopPrefix[1])) {
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case VEX_PREFIX_66:
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attrMask |= ATTR_OPSIZE;
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break;
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@ -784,7 +870,23 @@ static int getID(struct InternalInstruction* insn, const void *miiArg) {
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break;
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}
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if (lFromVEX2of2(insn->vexPrefix[1]))
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if (lFromVEX2of2(insn->vexXopPrefix[1]))
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attrMask |= ATTR_VEXL;
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}
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else if (insn->vexXopType == TYPE_XOP) {
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switch (ppFromXOP3of3(insn->vexXopPrefix[2])) {
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case VEX_PREFIX_66:
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attrMask |= ATTR_OPSIZE;
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break;
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case VEX_PREFIX_F3:
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attrMask |= ATTR_XS;
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break;
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case VEX_PREFIX_F2:
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attrMask |= ATTR_XD;
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break;
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}
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if (lFromXOP3of3(insn->vexXopPrefix[2]))
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attrMask |= ATTR_VEXL;
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}
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else {
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@ -1450,10 +1552,12 @@ static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
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static int readVVVV(struct InternalInstruction* insn) {
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dbgprintf(insn, "readVVVV()");
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if (insn->vexSize == 3)
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insn->vvvv = vvvvFromVEX3of3(insn->vexPrefix[2]);
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else if (insn->vexSize == 2)
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insn->vvvv = vvvvFromVEX2of2(insn->vexPrefix[1]);
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if (insn->vexXopType == TYPE_VEX_3B)
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insn->vvvv = vvvvFromVEX3of3(insn->vexXopPrefix[2]);
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else if (insn->vexXopType == TYPE_VEX_2B)
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insn->vvvv = vvvvFromVEX2of2(insn->vexXopPrefix[1]);
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else if (insn->vexXopType == TYPE_XOP)
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insn->vvvv = vvvvFromXOP3of3(insn->vexXopPrefix[2]);
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else
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return -1;
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@ -59,6 +59,15 @@ extern "C" {
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#define lFromVEX2of2(vex) (((vex) & 0x4) >> 2)
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#define ppFromVEX2of2(vex) ((vex) & 0x3)
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#define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7)
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#define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6)
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#define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5)
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#define mmmmmFromXOP2of3(xop) ((xop) & 0x1f)
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#define wFromXOP3of3(xop) (((xop) & 0x80) >> 7)
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#define vvvvFromXOP3of3(vex) (((~(vex)) & 0x78) >> 3)
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#define lFromXOP3of3(xop) (((xop) & 0x4) >> 2)
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#define ppFromXOP3of3(xop) ((xop) & 0x3)
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/*
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* These enums represent Intel registers for use by the decoder.
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*/
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@ -444,9 +453,15 @@ typedef enum {
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typedef enum {
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VEX_LOB_0F = 0x1,
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VEX_LOB_0F38 = 0x2,
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VEX_LOB_0F3A = 0x3
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VEX_LOB_0F3A = 0x3,
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} VEXLeadingOpcodeByte;
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typedef enum {
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XOP_MAP_SELECT_8 = 0x8,
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XOP_MAP_SELECT_9 = 0x9,
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XOP_MAP_SELECT_A = 0xA
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} XOPMapSelect;
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/*
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* VEXPrefixCode - Possible values for the VEX.pp field
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*/
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@ -458,6 +473,13 @@ typedef enum {
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VEX_PREFIX_F2 = 0x3
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} VEXPrefixCode;
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typedef enum {
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TYPE_NO_VEX_XOP = 0x0,
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TYPE_VEX_2B = 0x1,
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TYPE_VEX_3B = 0x2,
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TYPE_XOP = 0x3
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} VEXXOPType;
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typedef uint8_t BOOL;
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/*
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@ -514,10 +536,10 @@ struct InternalInstruction {
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uint8_t prefixPresent[0x100];
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/* contains the location (for use with the reader) of the prefix byte */
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uint64_t prefixLocations[0x100];
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/* The value of the VEX prefix, if present */
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uint8_t vexPrefix[3];
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/* The value of the VEX/XOP prefix, if present */
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uint8_t vexXopPrefix[3];
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/* The length of the VEX prefix (0 if not present) */
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uint8_t vexSize;
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VEXXOPType vexXopType;
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/* The value of the REX prefix, if present */
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uint8_t rexPrefix;
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/* The location where a mandatory prefix would have to be (i.e., right before
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@ -32,6 +32,9 @@
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#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes
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#define THREEBYTEA6_SYM x86DisassemblerThreeByteA6Opcodes
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#define THREEBYTEA7_SYM x86DisassemblerThreeByteA7Opcodes
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#define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes
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#define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes
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#define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes
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#define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers"
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#define CONTEXTS_STR "x86DisassemblerContexts"
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@ -41,6 +44,9 @@
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#define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes"
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#define THREEBYTEA6_STR "x86DisassemblerThreeByteA6Opcodes"
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#define THREEBYTEA7_STR "x86DisassemblerThreeByteA7Opcodes"
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#define XOP8_MAP_STR "x86DisassemblerXOP8Opcodes"
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#define XOP9_MAP_STR "x86DisassemblerXOP9Opcodes"
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#define XOPA_MAP_STR "x86DisassemblerXOPAOpcodes"
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/*
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* Attributes of an instruction that must be known before the opcode can be
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@ -234,7 +240,10 @@ typedef enum {
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THREEBYTE_38 = 2,
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THREEBYTE_3A = 3,
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THREEBYTE_A6 = 4,
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THREEBYTE_A7 = 5
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THREEBYTE_A7 = 5,
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XOP8_MAP = 6,
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XOP9_MAP = 7,
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XOPA_MAP = 8
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} OpcodeType;
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/*
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@ -1912,7 +1912,7 @@ let Predicates = [HasBMI2] in {
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//===----------------------------------------------------------------------===//
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// TBM Instructions
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//
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let isAsmParserOnly = 1, Predicates = [HasTBM], Defs = [EFLAGS] in {
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let Predicates = [HasTBM], Defs = [EFLAGS] in {
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multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
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X86MemOperand x86memop, PatFrag ld_frag,
|
||||
@ -1987,7 +1987,7 @@ defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m,
|
||||
defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m,
|
||||
int_x86_tbm_tzmsk_u32,
|
||||
int_x86_tbm_tzmsk_u64>;
|
||||
} // isAsmParserOnly, HasTBM, EFLAGS
|
||||
} // HasTBM, EFLAGS
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Pattern fragments to auto generate TBM instructions.
|
||||
|
||||
@ -20,23 +20,21 @@ multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
|
||||
[(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, VEX;
|
||||
}
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
defm VPHSUBWD : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, memopv2i64>;
|
||||
defm VPHSUBDQ : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, memopv2i64>;
|
||||
defm VPHSUBBW : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, memopv2i64>;
|
||||
defm VPHADDWQ : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, memopv2i64>;
|
||||
defm VPHADDWD : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, memopv2i64>;
|
||||
defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, memopv2i64>;
|
||||
defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, memopv2i64>;
|
||||
defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, memopv2i64>;
|
||||
defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, memopv2i64>;
|
||||
defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, memopv2i64>;
|
||||
defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, memopv2i64>;
|
||||
defm VPHADDDQ : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, memopv2i64>;
|
||||
defm VPHADDBW : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, memopv2i64>;
|
||||
defm VPHADDBQ : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, memopv2i64>;
|
||||
defm VPHADDBD : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, memopv2i64>;
|
||||
}
|
||||
defm VPHSUBWD : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, memopv2i64>;
|
||||
defm VPHSUBDQ : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, memopv2i64>;
|
||||
defm VPHSUBBW : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, memopv2i64>;
|
||||
defm VPHADDWQ : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, memopv2i64>;
|
||||
defm VPHADDWD : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, memopv2i64>;
|
||||
defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, memopv2i64>;
|
||||
defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, memopv2i64>;
|
||||
defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, memopv2i64>;
|
||||
defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, memopv2i64>;
|
||||
defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, memopv2i64>;
|
||||
defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, memopv2i64>;
|
||||
defm VPHADDDQ : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, memopv2i64>;
|
||||
defm VPHADDBW : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, memopv2i64>;
|
||||
defm VPHADDBQ : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, memopv2i64>;
|
||||
defm VPHADDBD : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, memopv2i64>;
|
||||
|
||||
// Scalar load 2 addr operand instructions
|
||||
multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
|
||||
@ -49,12 +47,10 @@ multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
|
||||
[(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, VEX;
|
||||
}
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss,
|
||||
ssmem, sse_load_f32>;
|
||||
defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd,
|
||||
sdmem, sse_load_f64>;
|
||||
}
|
||||
defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss,
|
||||
ssmem, sse_load_f32>;
|
||||
defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd,
|
||||
sdmem, sse_load_f64>;
|
||||
|
||||
multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
|
||||
PatFrag memop> {
|
||||
@ -66,10 +62,8 @@ multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
|
||||
[(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, VEX;
|
||||
}
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, memopv4f32>;
|
||||
defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, memopv2f64>;
|
||||
}
|
||||
defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, memopv4f32>;
|
||||
defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, memopv2f64>;
|
||||
|
||||
multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
|
||||
PatFrag memop> {
|
||||
@ -81,12 +75,8 @@ multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
|
||||
[(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, VEX, VEX_L;
|
||||
}
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256,
|
||||
memopv8f32>;
|
||||
defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256,
|
||||
memopv4f64>;
|
||||
}
|
||||
defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256, memopv8f32>;
|
||||
defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256, memopv4f64>;
|
||||
|
||||
multiclass xop3op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
|
||||
def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
|
||||
@ -107,20 +97,18 @@ multiclass xop3op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
|
||||
VEX_4VOp3;
|
||||
}
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
defm VPSHLW : xop3op<0x95, "vpshlw", int_x86_xop_vpshlw>;
|
||||
defm VPSHLQ : xop3op<0x97, "vpshlq", int_x86_xop_vpshlq>;
|
||||
defm VPSHLD : xop3op<0x96, "vpshld", int_x86_xop_vpshld>;
|
||||
defm VPSHLB : xop3op<0x94, "vpshlb", int_x86_xop_vpshlb>;
|
||||
defm VPSHAW : xop3op<0x99, "vpshaw", int_x86_xop_vpshaw>;
|
||||
defm VPSHAQ : xop3op<0x9B, "vpshaq", int_x86_xop_vpshaq>;
|
||||
defm VPSHAD : xop3op<0x9A, "vpshad", int_x86_xop_vpshad>;
|
||||
defm VPSHAB : xop3op<0x98, "vpshab", int_x86_xop_vpshab>;
|
||||
defm VPROTW : xop3op<0x91, "vprotw", int_x86_xop_vprotw>;
|
||||
defm VPROTQ : xop3op<0x93, "vprotq", int_x86_xop_vprotq>;
|
||||
defm VPROTD : xop3op<0x92, "vprotd", int_x86_xop_vprotd>;
|
||||
defm VPROTB : xop3op<0x90, "vprotb", int_x86_xop_vprotb>;
|
||||
}
|
||||
defm VPSHLW : xop3op<0x95, "vpshlw", int_x86_xop_vpshlw>;
|
||||
defm VPSHLQ : xop3op<0x97, "vpshlq", int_x86_xop_vpshlq>;
|
||||
defm VPSHLD : xop3op<0x96, "vpshld", int_x86_xop_vpshld>;
|
||||
defm VPSHLB : xop3op<0x94, "vpshlb", int_x86_xop_vpshlb>;
|
||||
defm VPSHAW : xop3op<0x99, "vpshaw", int_x86_xop_vpshaw>;
|
||||
defm VPSHAQ : xop3op<0x9B, "vpshaq", int_x86_xop_vpshaq>;
|
||||
defm VPSHAD : xop3op<0x9A, "vpshad", int_x86_xop_vpshad>;
|
||||
defm VPSHAB : xop3op<0x98, "vpshab", int_x86_xop_vpshab>;
|
||||
defm VPROTW : xop3op<0x91, "vprotw", int_x86_xop_vprotw>;
|
||||
defm VPROTQ : xop3op<0x93, "vprotq", int_x86_xop_vprotq>;
|
||||
defm VPROTD : xop3op<0x92, "vprotd", int_x86_xop_vprotd>;
|
||||
defm VPROTB : xop3op<0x90, "vprotb", int_x86_xop_vprotb>;
|
||||
|
||||
multiclass xop3opimm<bits<8> opc, string OpcodeStr, Intrinsic Int> {
|
||||
def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
|
||||
@ -134,12 +122,10 @@ multiclass xop3opimm<bits<8> opc, string OpcodeStr, Intrinsic Int> {
|
||||
(Int (bitconvert (memopv2i64 addr:$src1)), imm:$src2))]>, VEX;
|
||||
}
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
defm VPROTW : xop3opimm<0xC1, "vprotw", int_x86_xop_vprotwi>;
|
||||
defm VPROTQ : xop3opimm<0xC3, "vprotq", int_x86_xop_vprotqi>;
|
||||
defm VPROTD : xop3opimm<0xC2, "vprotd", int_x86_xop_vprotdi>;
|
||||
defm VPROTB : xop3opimm<0xC0, "vprotb", int_x86_xop_vprotbi>;
|
||||
}
|
||||
defm VPROTW : xop3opimm<0xC1, "vprotw", int_x86_xop_vprotwi>;
|
||||
defm VPROTQ : xop3opimm<0xC3, "vprotq", int_x86_xop_vprotqi>;
|
||||
defm VPROTD : xop3opimm<0xC2, "vprotd", int_x86_xop_vprotdi>;
|
||||
defm VPROTB : xop3opimm<0xC0, "vprotb", int_x86_xop_vprotbi>;
|
||||
|
||||
// Instruction where second source can be memory, but third must be register
|
||||
multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> {
|
||||
@ -158,20 +144,18 @@ multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> {
|
||||
VR128:$src3))]>, VEX_4V, VEX_I8IMM;
|
||||
}
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
defm VPMADCSWD : xop4opm2<0xB6, "vpmadcswd", int_x86_xop_vpmadcswd>;
|
||||
defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", int_x86_xop_vpmadcsswd>;
|
||||
defm VPMACSWW : xop4opm2<0x95, "vpmacsww", int_x86_xop_vpmacsww>;
|
||||
defm VPMACSWD : xop4opm2<0x96, "vpmacswd", int_x86_xop_vpmacswd>;
|
||||
defm VPMACSSWW : xop4opm2<0x85, "vpmacssww", int_x86_xop_vpmacssww>;
|
||||
defm VPMACSSWD : xop4opm2<0x86, "vpmacsswd", int_x86_xop_vpmacsswd>;
|
||||
defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", int_x86_xop_vpmacssdql>;
|
||||
defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", int_x86_xop_vpmacssdqh>;
|
||||
defm VPMACSSDD : xop4opm2<0x8E, "vpmacssdd", int_x86_xop_vpmacssdd>;
|
||||
defm VPMACSDQL : xop4opm2<0x97, "vpmacsdql", int_x86_xop_vpmacsdql>;
|
||||
defm VPMACSDQH : xop4opm2<0x9F, "vpmacsdqh", int_x86_xop_vpmacsdqh>;
|
||||
defm VPMACSDD : xop4opm2<0x9E, "vpmacsdd", int_x86_xop_vpmacsdd>;
|
||||
}
|
||||
defm VPMADCSWD : xop4opm2<0xB6, "vpmadcswd", int_x86_xop_vpmadcswd>;
|
||||
defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", int_x86_xop_vpmadcsswd>;
|
||||
defm VPMACSWW : xop4opm2<0x95, "vpmacsww", int_x86_xop_vpmacsww>;
|
||||
defm VPMACSWD : xop4opm2<0x96, "vpmacswd", int_x86_xop_vpmacswd>;
|
||||
defm VPMACSSWW : xop4opm2<0x85, "vpmacssww", int_x86_xop_vpmacssww>;
|
||||
defm VPMACSSWD : xop4opm2<0x86, "vpmacsswd", int_x86_xop_vpmacsswd>;
|
||||
defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", int_x86_xop_vpmacssdql>;
|
||||
defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", int_x86_xop_vpmacssdqh>;
|
||||
defm VPMACSSDD : xop4opm2<0x8E, "vpmacssdd", int_x86_xop_vpmacssdd>;
|
||||
defm VPMACSDQL : xop4opm2<0x97, "vpmacsdql", int_x86_xop_vpmacsdql>;
|
||||
defm VPMACSDQH : xop4opm2<0x9F, "vpmacsdqh", int_x86_xop_vpmacsdqh>;
|
||||
defm VPMACSDD : xop4opm2<0x9E, "vpmacsdd", int_x86_xop_vpmacsdd>;
|
||||
|
||||
// Instruction where second source can be memory, third must be imm8
|
||||
multiclass xop4opimm<bits<8> opc, string OpcodeStr, Intrinsic Int> {
|
||||
@ -190,16 +174,14 @@ multiclass xop4opimm<bits<8> opc, string OpcodeStr, Intrinsic Int> {
|
||||
imm:$src3))]>, VEX_4V;
|
||||
}
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
defm VPCOMB : xop4opimm<0xCC, "vpcomb", int_x86_xop_vpcomb>;
|
||||
defm VPCOMW : xop4opimm<0xCD, "vpcomw", int_x86_xop_vpcomw>;
|
||||
defm VPCOMD : xop4opimm<0xCE, "vpcomd", int_x86_xop_vpcomd>;
|
||||
defm VPCOMQ : xop4opimm<0xCF, "vpcomq", int_x86_xop_vpcomq>;
|
||||
defm VPCOMUB : xop4opimm<0xEC, "vpcomub", int_x86_xop_vpcomub>;
|
||||
defm VPCOMUW : xop4opimm<0xED, "vpcomuw", int_x86_xop_vpcomuw>;
|
||||
defm VPCOMUD : xop4opimm<0xEE, "vpcomud", int_x86_xop_vpcomud>;
|
||||
defm VPCOMUQ : xop4opimm<0xEF, "vpcomuq", int_x86_xop_vpcomuq>;
|
||||
}
|
||||
defm VPCOMB : xop4opimm<0xCC, "vpcomb", int_x86_xop_vpcomb>;
|
||||
defm VPCOMW : xop4opimm<0xCD, "vpcomw", int_x86_xop_vpcomw>;
|
||||
defm VPCOMD : xop4opimm<0xCE, "vpcomd", int_x86_xop_vpcomd>;
|
||||
defm VPCOMQ : xop4opimm<0xCF, "vpcomq", int_x86_xop_vpcomq>;
|
||||
defm VPCOMUB : xop4opimm<0xEC, "vpcomub", int_x86_xop_vpcomub>;
|
||||
defm VPCOMUW : xop4opimm<0xED, "vpcomuw", int_x86_xop_vpcomuw>;
|
||||
defm VPCOMUD : xop4opimm<0xEE, "vpcomud", int_x86_xop_vpcomud>;
|
||||
defm VPCOMUQ : xop4opimm<0xEF, "vpcomuq", int_x86_xop_vpcomuq>;
|
||||
|
||||
// Instruction where either second or third source can be memory
|
||||
multiclass xop4op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
|
||||
@ -227,10 +209,8 @@ multiclass xop4op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
|
||||
VEX_4V, VEX_I8IMM;
|
||||
}
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
defm VPPERM : xop4op<0xA3, "vpperm", int_x86_xop_vpperm>;
|
||||
defm VPCMOV : xop4op<0xA2, "vpcmov", int_x86_xop_vpcmov>;
|
||||
}
|
||||
defm VPPERM : xop4op<0xA3, "vpperm", int_x86_xop_vpperm>;
|
||||
defm VPCMOV : xop4op<0xA2, "vpcmov", int_x86_xop_vpcmov>;
|
||||
|
||||
multiclass xop4op256<bits<8> opc, string OpcodeStr, Intrinsic Int> {
|
||||
def rrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
|
||||
@ -257,9 +237,7 @@ multiclass xop4op256<bits<8> opc, string OpcodeStr, Intrinsic Int> {
|
||||
VEX_4V, VEX_I8IMM, VEX_L;
|
||||
}
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
defm VPCMOV : xop4op256<0xA2, "vpcmov", int_x86_xop_vpcmov_256>;
|
||||
}
|
||||
defm VPCMOV : xop4op256<0xA2, "vpcmov", int_x86_xop_vpcmov_256>;
|
||||
|
||||
multiclass xop5op<bits<8> opc, string OpcodeStr, Intrinsic Int128,
|
||||
Intrinsic Int256, PatFrag ld_128, PatFrag ld_256> {
|
||||
|
||||
@ -770,9 +770,24 @@
|
||||
# CHECK: vfmaddps %ymm2, %ymm1, %ymm0, %ymm0
|
||||
0xc4 0xe3 0xfd 0x68 0xc2 0x10
|
||||
|
||||
# CHECK: vpermil2ps $0, %xmm4, %xmm3, %xmm2, %xmm1
|
||||
0xc4 0xe3 0x69 0x48 0xcb 0x40
|
||||
|
||||
# CHECK: vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0
|
||||
0xc4 0xe3 0xe1 0x48 0x40 0x04 0x21
|
||||
|
||||
# CHECK: vpermil2ps $2, (%rax), %ymm1, %ymm5, %ymm6
|
||||
0xc4 0xe3 0xd5 0x48 0x30 0x12
|
||||
|
||||
# CHECK: vpermil2ps $3, %xmm1, (%rax), %xmm3, %xmm4
|
||||
0xc4 0xe3 0x61 0x48 0x20 0x13
|
||||
|
||||
# CHECK: vpermil2ps $0, %ymm4, %ymm4, %ymm2, %ymm2
|
||||
0xc4 0xe3 0x6d 0x48 0xd4 0x40
|
||||
|
||||
# CHECK: vpermil2pd $1, %ymm1, 4(%rax), %ymm1, %ymm0
|
||||
0xc4 0xe3 0x75 0x49 0x40 0x04 0x11
|
||||
|
||||
# CHECK: vgatherdpd %xmm0, (%rdi,%xmm1,2), %xmm2
|
||||
0xc4 0xe2 0xf9 0x92 0x14 0x4f
|
||||
|
||||
@ -844,3 +859,60 @@
|
||||
# CHECK: xacquire
|
||||
# CHECK-NEXT: xchgl %ebx, (%rax)
|
||||
0xf2 0x87 0x18
|
||||
|
||||
# CHECK: bextr $2814, %edi, %eax
|
||||
0x8f 0xea 0x78 0x10 0xc7 0xfe 0x0a 0x00 0x00
|
||||
|
||||
# CHECK: blci %rdi, %rax
|
||||
0x8f 0xe9 0xf8 0x02 0xf7
|
||||
|
||||
# CHECK: vpcmov %xmm1, %xmm2, %xmm3, %xmm4
|
||||
0x8f 0xe8 0x60 0xa2 0xe2 0x10
|
||||
|
||||
# CHECK: vpcmov (%rax), %xmm2, %xmm3, %xmm4
|
||||
0x8f 0xe8 0xe0 0xa2 0x20 0x20
|
||||
|
||||
# CHECK: vpcmov %xmm1, (%rax), %xmm3, %xmm4
|
||||
0x8f 0xe8 0x60 0xa2 0x20 0x10
|
||||
|
||||
# CHECK: vpcmov %ymm1, %ymm2, %ymm3, %ymm4
|
||||
0x8f 0xe8 0x64 0xa2 0xe2 0x10
|
||||
|
||||
# CHECK: vpcmov (%rax), %ymm2, %ymm3, %ymm4
|
||||
0x8f 0xe8 0xe4 0xa2 0x20 0x20
|
||||
|
||||
# CHECK: vpcmov %ymm1, (%rax), %ymm3, %ymm4
|
||||
0x8f 0xe8 0x64 0xa2 0x20 0x10
|
||||
|
||||
# CHECK: vpcomb $55, %xmm6, %xmm4, %xmm2
|
||||
0x8f 0xe8 0x58 0xcc 0xd6 0x37
|
||||
|
||||
# CHECK: vpcomb $56, 8(%rax), %xmm3, %xmm2
|
||||
0x8f 0xe8 0x60 0xcc 0x50 0x08 0x38
|
||||
|
||||
# CHECK: vpmacsdd %xmm4, %xmm6, %xmm4, %xmm2
|
||||
0x8f 0xe8 0x58 0x9e 0xd6 0x40
|
||||
# CHECK: vpmacsdd %xmm4, (%rax,%rcx), %xmm4, %xmm3
|
||||
0x8f 0xe8 0x58 0x9e 0x1c 0x08 0x40
|
||||
|
||||
# CHECK: vprotd (%rax), %xmm0, %xmm3
|
||||
0x8f 0xe9 0xf8 0x92 0x18
|
||||
# CHECK: vprotd %xmm2, (%rax,%rcx), %xmm4
|
||||
0x8f 0xe9 0x68 0x92 0x24 0x08
|
||||
# CHECK: vprotd %xmm5, %xmm3, %xmm2
|
||||
0x8f 0xe9 0x50 0x92 0xd3
|
||||
# CHECK: vprotd $43, (%rcx), %xmm6
|
||||
0x8f 0xe8 0x78 0xc2 0x31 0x2b
|
||||
# CHECK: vprotd $44, (%rax,%rcx), %xmm7
|
||||
0x8f 0xe8 0x78 0xc2 0x3c 0x08 0x2c
|
||||
# CHECK: vprotd $45, %xmm4, %xmm4
|
||||
0x8f 0xe8 0x78 0xc2 0xe4 0x2d
|
||||
|
||||
# CHECK: vfrczps 4(%rax), %xmm3
|
||||
0x8f 0xe9 0x78 0x80 0x58 0x04
|
||||
# CHECK: vfrczps %xmm6, %xmm5
|
||||
0x8f 0xe9 0x78 0x80 0xee
|
||||
# CHECK: vfrczps (%rcx), %xmm1
|
||||
0x8f 0xe9 0x78 0x80 0x09
|
||||
# CHECK: vfrczps %ymm2, %ymm4
|
||||
0x8f 0xe9 0x7c 0x80 0xe2
|
||||
|
||||
@ -42,4 +42,4 @@ vpbroadcastd %xmm0, %zmm1 {%k1} {z}
|
||||
|
||||
// CHECK: vmovdqu64 {{.*}} {%k3}
|
||||
// CHECK: encoding: [0x62,0xf1,0xfe,0x4b,0x6f,0xc8]
|
||||
vmovdqu64 %zmm0, %zmm1 {%k3}
|
||||
vmovdqu64 %zmm0, %zmm1 {%k3}
|
||||
|
||||
@ -707,6 +707,9 @@ void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
|
||||
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
|
||||
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], THREEBYTEA6_STR);
|
||||
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], THREEBYTEA7_STR);
|
||||
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOP8_MAP_STR);
|
||||
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[7], XOP9_MAP_STR);
|
||||
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[8], XOPA_MAP_STR);
|
||||
}
|
||||
|
||||
void DisassemblerTables::emit(raw_ostream &o) const {
|
||||
|
||||
@ -40,7 +40,10 @@ private:
|
||||
/// [3] three-byte opcodes of the form 0f 3a __
|
||||
/// [4] three-byte opcodes of the form 0f a6 __
|
||||
/// [5] three-byte opcodes of the form 0f a7 __
|
||||
ContextDecision* Tables[6];
|
||||
/// [6] XOP8 map opcode
|
||||
/// [7] XOP9 map opcode
|
||||
/// [8] XOPA map opcode
|
||||
ContextDecision* Tables[9];
|
||||
|
||||
// Table of ModRM encodings.
|
||||
typedef std::map<std::vector<unsigned>, unsigned> ModRMMapTy;
|
||||
|
||||
@ -79,7 +79,8 @@ namespace X86Local {
|
||||
DC = 7, DD = 8, DE = 9, DF = 10,
|
||||
XD = 11, XS = 12,
|
||||
T8 = 13, P_TA = 14,
|
||||
A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
|
||||
A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
|
||||
XOP8 = 20, XOP9 = 21, XOPA = 22
|
||||
};
|
||||
}
|
||||
|
||||
@ -134,6 +135,10 @@ namespace X86Local {
|
||||
#define THREE_BYTE_38_EXTENSION_TABLES \
|
||||
EXTENSION_TABLE(F3)
|
||||
|
||||
#define XOP9_MAP_EXTENSION_TABLES \
|
||||
EXTENSION_TABLE(01) \
|
||||
EXTENSION_TABLE(02)
|
||||
|
||||
using namespace X86Disassembler;
|
||||
|
||||
/// needsModRMForDecode - Indicates whether a particular instruction requires a
|
||||
@ -908,6 +913,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
|
||||
uint8_t opcodeToSet = 0;
|
||||
|
||||
switch (Prefix) {
|
||||
default: llvm_unreachable("Invalid prefix!");
|
||||
// Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
|
||||
case X86Local::XD:
|
||||
case X86Local::XS:
|
||||
@ -1021,6 +1027,63 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
|
||||
filter = new DumbFilter();
|
||||
opcodeToSet = Opcode;
|
||||
break;
|
||||
case X86Local::XOP8:
|
||||
opcodeType = XOP8_MAP;
|
||||
if (needsModRMForDecode(Form))
|
||||
filter = new ModFilter(isRegFormat(Form));
|
||||
else
|
||||
filter = new DumbFilter();
|
||||
opcodeToSet = Opcode;
|
||||
break;
|
||||
case X86Local::XOP9:
|
||||
opcodeType = XOP9_MAP;
|
||||
switch (Opcode) {
|
||||
default:
|
||||
if (needsModRMForDecode(Form))
|
||||
filter = new ModFilter(isRegFormat(Form));
|
||||
else
|
||||
filter = new DumbFilter();
|
||||
break;
|
||||
#define EXTENSION_TABLE(n) case 0x##n:
|
||||
XOP9_MAP_EXTENSION_TABLES
|
||||
#undef EXTENSION_TABLE
|
||||
switch (Form) {
|
||||
default:
|
||||
llvm_unreachable("Unhandled XOP9 extended opcode");
|
||||
case X86Local::MRM0r:
|
||||
case X86Local::MRM1r:
|
||||
case X86Local::MRM2r:
|
||||
case X86Local::MRM3r:
|
||||
case X86Local::MRM4r:
|
||||
case X86Local::MRM5r:
|
||||
case X86Local::MRM6r:
|
||||
case X86Local::MRM7r:
|
||||
filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
|
||||
break;
|
||||
case X86Local::MRM0m:
|
||||
case X86Local::MRM1m:
|
||||
case X86Local::MRM2m:
|
||||
case X86Local::MRM3m:
|
||||
case X86Local::MRM4m:
|
||||
case X86Local::MRM5m:
|
||||
case X86Local::MRM6m:
|
||||
case X86Local::MRM7m:
|
||||
filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
|
||||
break;
|
||||
MRM_MAPPING
|
||||
} // switch (Form)
|
||||
break;
|
||||
} // switch (Opcode)
|
||||
opcodeToSet = Opcode;
|
||||
break;
|
||||
case X86Local::XOPA:
|
||||
opcodeType = XOPA_MAP;
|
||||
if (needsModRMForDecode(Form))
|
||||
filter = new ModFilter(isRegFormat(Form));
|
||||
else
|
||||
filter = new DumbFilter();
|
||||
opcodeToSet = Opcode;
|
||||
break;
|
||||
case X86Local::D8:
|
||||
case X86Local::D9:
|
||||
case X86Local::DA:
|
||||
@ -1041,7 +1104,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
|
||||
opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
|
||||
break;
|
||||
case X86Local::REP:
|
||||
default:
|
||||
case 0:
|
||||
opcodeType = ONEBYTE;
|
||||
switch (Opcode) {
|
||||
#define EXTENSION_TABLE(n) case 0x##n:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user