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R600/SI: Add generic checks to SIInstrInfo::verifyInstruction()
Added checks for number of operands and operand register classes. Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204054 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -377,6 +377,47 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
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int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
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int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
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int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
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int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
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// Make sure the number of operands is correct.
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const MCInstrDesc &Desc = get(Opcode);
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if (!Desc.isVariadic() &&
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Desc.getNumOperands() != MI->getNumExplicitOperands()) {
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ErrInfo = "Instruction has wrong number of operands.";
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return false;
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}
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// Make sure the register classes are correct
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for (unsigned i = 0, e = Desc.getNumOperands(); i != e; ++i) {
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switch (Desc.OpInfo[i].OperandType) {
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case MCOI::OPERAND_REGISTER:
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break;
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case MCOI::OPERAND_IMMEDIATE:
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if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm()) {
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ErrInfo = "Expected immediate, but got non-immediate";
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return false;
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}
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// Fall-through
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default:
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continue;
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}
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if (!MI->getOperand(i).isReg())
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continue;
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int RegClass = Desc.OpInfo[i].RegClass;
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if (RegClass != -1) {
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unsigned Reg = MI->getOperand(i).getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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const TargetRegisterClass *RC = RI.getRegClass(RegClass);
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if (!RC->contains(Reg)) {
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ErrInfo = "Operand has incorrect register class.";
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return false;
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}
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}
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}
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// Verify VOP*
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// Verify VOP*
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if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
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if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
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unsigned ConstantBusCount = 0;
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unsigned ConstantBusCount = 0;
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