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[SKX] Enabling mask logic instructions: encoding, lowering
Instructions: KAND{BWDQ}, KANDN{BWDQ}, KOR{BWDQ}, KXOR{BWDQ}, KXNOR{BWDQ} Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214081 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1247,31 +1247,38 @@ def : Pat<(not VK8:$src),
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// Mask binary operation
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// - KAND, KANDN, KOR, KXNOR, KXOR
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multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
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RegisterClass KRC, SDPatternOperator OpNode> {
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let Predicates = [HasAVX512] in
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RegisterClass KRC, SDPatternOperator OpNode,
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Predicate prd> {
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let Predicates = [prd] in
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def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
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!strconcat(OpcodeStr,
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" \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
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}
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multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
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SDPatternOperator OpNode> {
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defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
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VEX_4V, VEX_L, PS;
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multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
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SDPatternOperator OpNode> {
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defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
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HasDQI>, VEX_4V, VEX_L, PD;
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defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
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HasAVX512>, VEX_4V, VEX_L, PS;
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defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
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HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
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defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
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HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
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}
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def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
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def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
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let isCommutable = 1 in {
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defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
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let isCommutable = 0 in
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defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
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defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
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defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
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defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
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defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
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defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
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defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
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defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
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}
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let isCommutable = 0 in
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defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
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def : Pat<(xor VK1:$src1, VK1:$src2),
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(COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=x86-64 -mcpu=knl | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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define i16 @mask16(i16 %x) {
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%m0 = bitcast i16 %x to <16 x i1>
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=x86-64 -mcpu=skx | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s
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define i32 @mask32(i32 %x) {
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%m0 = bitcast i32 %x to <32 x i1>
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@ -71,3 +71,29 @@ define void @mask64_mem(i64* %ptr) {
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; CHECK-NEXT: kmovq %k{{[0-7]}}, ([[ARG1]])
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; CHECK_NEXT: ret
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}
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define i32 @mand32(i32 %x, i32 %y) {
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%ma = bitcast i32 %x to <32 x i1>
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%mb = bitcast i32 %y to <32 x i1>
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%mc = and <32 x i1> %ma, %mb
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%md = xor <32 x i1> %ma, %mb
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%me = or <32 x i1> %mc, %md
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%ret = bitcast <32 x i1> %me to i32
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; CHECK: kandd
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; CHECK: kxord
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; CHECK: kord
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ret i32 %ret
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}
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define i64 @mand64(i64 %x, i64 %y) {
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%ma = bitcast i64 %x to <64 x i1>
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%mb = bitcast i64 %y to <64 x i1>
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%mc = and <64 x i1> %ma, %mb
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%md = xor <64 x i1> %ma, %mb
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%me = or <64 x i1> %mc, %md
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%ret = bitcast <64 x i1> %me to i64
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; CHECK: kandq
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; CHECK: kxorq
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; CHECK: korq
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ret i64 %ret
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}
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=x86-64 -mcpu=skx | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s
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define i8 @mask8(i8 %x) {
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%m0 = bitcast i8 %x to <8 x i1>
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@ -23,3 +23,16 @@ define void @mask8_mem(i8* %ptr) {
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; CHECK-NEXT: kmovb %k{{[0-7]}}, ([[ARG1]])
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; CHECK: ret
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}
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define i8 @mand8(i8 %x, i8 %y) {
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%ma = bitcast i8 %x to <8 x i1>
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%mb = bitcast i8 %y to <8 x i1>
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%mc = and <8 x i1> %ma, %mb
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%md = xor <8 x i1> %ma, %mb
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%me = or <8 x i1> %mc, %md
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%ret = bitcast <8 x i1> %me to i8
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; CHECK: kandb
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; CHECK: kxorb
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; CHECK: korb
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ret i8 %ret
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}
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@ -2489,6 +2489,26 @@
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// CHECK: encoding: [0x62,0x71,0x24,0x50,0x5c,0xb2,0xfc,0xfd,0xff,0xff]
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vsubps -516(%rdx){1to16}, %zmm27, %zmm14
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// CHECK: kandw %k6, %k5, %k2
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// CHECK: encoding: [0xc5,0xd4,0x41,0xd6]
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kandw %k6, %k5, %k2
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// CHECK: kandnw %k7, %k6, %k4
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// CHECK: encoding: [0xc5,0xcc,0x42,0xe7]
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kandnw %k7, %k6, %k4
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// CHECK: korw %k7, %k6, %k4
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// CHECK: encoding: [0xc5,0xcc,0x45,0xe7]
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korw %k7, %k6, %k4
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// CHECK: kxnorw %k5, %k5, %k3
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// CHECK: encoding: [0xc5,0xd4,0x46,0xdd]
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kxnorw %k5, %k5, %k3
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// CHECK: kxorw %k7, %k6, %k2
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// CHECK: encoding: [0xc5,0xcc,0x47,0xd7]
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kxorw %k7, %k6, %k2
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// CHECK: knotw %k6, %k3
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// CHECK: encoding: [0xc5,0xf8,0x44,0xde]
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knotw %k6, %k3
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@ -1,5 +1,45 @@
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// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=skx --show-encoding %s | FileCheck %s
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// CHECK: kandq %k7, %k5, %k5
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// CHECK: encoding: [0xc4,0xe1,0xd4,0x41,0xef]
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kandq %k7, %k5, %k5
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// CHECK: kandd %k4, %k5, %k5
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// CHECK: encoding: [0xc4,0xe1,0xd5,0x41,0xec]
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kandd %k4, %k5, %k5
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// CHECK: kandnq %k4, %k5, %k2
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// CHECK: encoding: [0xc4,0xe1,0xd4,0x42,0xd4]
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kandnq %k4, %k5, %k2
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// CHECK: kandnd %k6, %k6, %k3
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// CHECK: encoding: [0xc4,0xe1,0xcd,0x42,0xde]
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kandnd %k6, %k6, %k3
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// CHECK: korq %k4, %k5, %k4
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// CHECK: encoding: [0xc4,0xe1,0xd4,0x45,0xe4]
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korq %k4, %k5, %k4
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// CHECK: kord %k6, %k6, %k5
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// CHECK: encoding: [0xc4,0xe1,0xcd,0x45,0xee]
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kord %k6, %k6, %k5
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// CHECK: kxnorq %k6, %k5, %k2
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// CHECK: encoding: [0xc4,0xe1,0xd4,0x46,0xd6]
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kxnorq %k6, %k5, %k2
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// CHECK: kxnord %k5, %k3, %k5
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// CHECK: encoding: [0xc4,0xe1,0xe5,0x46,0xed]
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kxnord %k5, %k3, %k5
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// CHECK: kxorq %k4, %k3, %k2
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// CHECK: encoding: [0xc4,0xe1,0xe4,0x47,0xd4]
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kxorq %k4, %k3, %k2
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// CHECK: kxord %k6, %k5, %k2
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// CHECK: encoding: [0xc4,0xe1,0xd5,0x47,0xd6]
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kxord %k6, %k5, %k2
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// CHECK: knotq %k6, %k3
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// CHECK: encoding: [0xc4,0xe1,0xf8,0x44,0xde]
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knotq %k6, %k3
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// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=skx --show-encoding %s | FileCheck %s
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// CHECK: kandb %k6, %k5, %k2
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// CHECK: encoding: [0xc5,0xd5,0x41,0xd6]
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kandb %k6, %k5, %k2
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// CHECK: kandnb %k4, %k6, %k5
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// CHECK: encoding: [0xc5,0xcd,0x42,0xec]
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kandnb %k4, %k6, %k5
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// CHECK: korb %k5, %k4, %k4
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// CHECK: encoding: [0xc5,0xdd,0x45,0xe5]
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korb %k5, %k4, %k4
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// CHECK: kxnorb %k7, %k6, %k4
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// CHECK: encoding: [0xc5,0xcd,0x46,0xe7]
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kxnorb %k7, %k6, %k4
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// CHECK: kxorb %k5, %k6, %k4
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// CHECK: encoding: [0xc5,0xcd,0x47,0xe5]
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kxorb %k5, %k6, %k4
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// CHECK: knotb %k4, %k5
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// CHECK: encoding: [0xc5,0xf9,0x44,0xec]
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knotb %k4, %k5
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// CHECK: knotb %k3, %k3
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// CHECK: encoding: [0xc5,0xf9,0x44,0xdb]
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knotb %k3, %k3
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@ -1117,6 +1117,8 @@ RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
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ENCODING("VK4", ENCODING_VVVV)
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ENCODING("VK8", ENCODING_VVVV)
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ENCODING("VK16", ENCODING_VVVV)
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ENCODING("VK32", ENCODING_VVVV)
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ENCODING("VK64", ENCODING_VVVV)
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errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
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llvm_unreachable("Unhandled VEX.vvvv register encoding");
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}
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