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MRegisterInfo.h - Added prototypes for functions we need to map a register to

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an appropriate TargetRegisterClass, also adds TargetRegisterClass definition.
TargetMachine.h - speling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4781 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2002-11-20 18:54:53 +00:00
parent cfe487296c
commit 282ec57c4c
2 changed files with 50 additions and 6 deletions
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52
include/llvm/Target/MRegisterInfo.h
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@ -6,11 +6,14 @@
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_MREGISTERINFO_H
#define LLVM_CODEGEN_MREGISTERINFO_H
#ifndef LLVM_TARGET_MREGISTERINFO_H
#define LLVM_TARGET_MREGISTERINFO_H
#include "llvm/CodeGen/MachineBasicBlock.h"
#include <assert.h>
class Type;
/// MRegisterDesc - This record contains all of the information known about a
/// particular register.
///
@ -38,6 +41,30 @@ namespace MRF { // MRF = Machine Register Flags
};
};
class TargetRegisterClass {
protected:
TargetRegisterClass() {}
public:
typedef unsigned* iterator;
typedef unsigned* const_iterator;
iterator begin();
iterator end();
const_iterator begin() const;
const_iterator end() const;
virtual unsigned getNumRegs() const { return 0; }
virtual unsigned getRegister(unsigned idx) const { return 0; }
virtual unsigned getDataSize() const { return 0; }
//const std::vector<unsigned> &getRegsInClass(void) { return Regs; }
//void getAliases(void);
};
/// MRegisterInfo base class - We assume that the target defines a static array
/// of MRegisterDesc objects that represent all of the machine registers that
/// the target has. As such, we simply have to track a pointer to this array so
@ -79,8 +106,25 @@ public:
///
const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
// This will eventually get some virtual methods...
virtual void copyReg2PCRel(MachineBasicBlock *MBB,
MachineBasicBlock::iterator &MBBI,
unsigned SrcReg, unsigned ImmOffset,
unsigned dataSize) const = 0;
virtual void copyPCRel2Reg(MachineBasicBlock *MBB,
MachineBasicBlock::iterator &MBBI,
unsigned ImmOffset, unsigned DestReg,
unsigned dataSize) const = 0;
/// Register class iterators
typedef const TargetRegisterClass* const_iterator;
virtual const_iterator const_regclass_begin() const = 0;
virtual const_iterator const_regclass_end() const = 0;
virtual unsigned getNumRegClasses() const = 0;
virtual const TargetRegisterClass* getRegClassForType(const Type* Ty) const=0;
};
#endif

4
include/llvm/Target/TargetMachine.h
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@ -1,4 +1,4 @@
//===-- llvm/Target/Machine.h - General Target Information -------*- C++ -*-==//
//===-- llvm/Target/TargetMachine.h - General Target Information -*- C++ -*-==//
//
// This file describes the general parts of a Target machine.
//
@ -68,7 +68,7 @@ public:
virtual const MachineOptInfo& getOptInfo() const = 0;
/// getRegisterInfo - If register information is available, return it. If
/// not, return null. This is kept seperate from RegInfo until RegInfo gets
/// not, return null. This is kept separate from RegInfo until RegInfo gets
/// straightened out.
///
virtual const MRegisterInfo* getRegisterInfo() const { return 0; }