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Make it possible for the Subtarget to change between function

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passes in the mips back end. This, unfortunately, required a
bit of churn in the various predicates to use a pointer rather
than a reference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212744 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
2014-07-10 17:26:51 +00:00
parent 5b8419d32e
commit 282eda9b74
9 changed files with 57 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/Mips/Mips16ISelDAGToDAG.cpp
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@@ -37,7 +37,7 @@ using namespace llvm;
#define DEBUG_TYPE "mips-isel" #define DEBUG_TYPE "mips-isel"
bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
if (!Subtarget.inMips16Mode()) if (!Subtarget->inMips16Mode())
return false; return false;
return MipsDAGToDAGISel::runOnMachineFunction(MF); return MipsDAGToDAGISel::runOnMachineFunction(MF);
} }
@@ -226,9 +226,9 @@ bool Mips16DAGToDAGISel::selectAddr16(
const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent); const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
if (LS) { if (LS) {
if (LS->getMemoryVT() == MVT::f32 && Subtarget.hasMips4_32r2()) if (LS->getMemoryVT() == MVT::f32 && Subtarget->hasMips4_32r2())
return false; return false;
if (LS->getMemoryVT() == MVT::f64 && Subtarget.hasMips4_32r2()) if (LS->getMemoryVT() == MVT::f64 && Subtarget->hasMips4_32r2())
return false; return false;
} }
} }

4
lib/Target/Mips/MipsDSPInstrFormats.td
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@@ -7,9 +7,9 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def HasDSP : Predicate<"Subtarget.hasDSP()">, def HasDSP : Predicate<"Subtarget->hasDSP()">,
AssemblerPredicate<"FeatureDSP">; AssemblerPredicate<"FeatureDSP">;
def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">, def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
AssemblerPredicate<"FeatureDSPR2">; AssemblerPredicate<"FeatureDSPR2">;
// Fields. // Fields.

8
lib/Target/Mips/MipsFastISel.cpp
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@@ -41,7 +41,7 @@ class MipsFastISel final : public FastISel {
const TargetMachine &TM; const TargetMachine &TM;
const TargetInstrInfo &TII; const TargetInstrInfo &TII;
const TargetLowering &TLI; const TargetLowering &TLI;
const MipsSubtarget &Subtarget; const MipsSubtarget *Subtarget;
MipsFunctionInfo *MFI; MipsFunctionInfo *MFI;
// Convenience variables to avoid some queries. // Convenience variables to avoid some queries.
@@ -56,11 +56,11 @@ public:
M(const_cast<Module &>(*funcInfo.Fn->getParent())), M(const_cast<Module &>(*funcInfo.Fn->getParent())),
TM(funcInfo.MF->getTarget()), TII(*TM.getInstrInfo()), TM(funcInfo.MF->getTarget()), TII(*TM.getInstrInfo()),
TLI(*TM.getTargetLowering()), TLI(*TM.getTargetLowering()),
Subtarget(TM.getSubtarget<MipsSubtarget>()) { Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
MFI = funcInfo.MF->getInfo<MipsFunctionInfo>(); MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
Context = &funcInfo.Fn->getContext(); Context = &funcInfo.Fn->getContext();
TargetSupported = ((Subtarget.getRelocationModel() == Reloc::PIC_) && TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
(Subtarget.hasMips32r2() && (Subtarget.isABI_O32()))); (Subtarget->hasMips32r2() && (Subtarget->isABI_O32())));
} }
bool TargetSelectInstruction(const Instruction *I) override; bool TargetSelectInstruction(const Instruction *I) override;

3
lib/Target/Mips/MipsISelDAGToDAG.cpp
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@@ -47,6 +47,7 @@ using namespace llvm;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &TM.getSubtarget<MipsSubtarget>();
bool Ret = SelectionDAGISel::runOnMachineFunction(MF); bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
processFunctionAfterISel(MF); processFunctionAfterISel(MF);
@@ -202,7 +203,7 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
#ifndef NDEBUG #ifndef NDEBUG
case ISD::LOAD: case ISD::LOAD:
case ISD::STORE: case ISD::STORE:
assert((Subtarget.systemSupportsUnalignedAccess() || assert((Subtarget->systemSupportsUnalignedAccess() ||
cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <= cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
cast<MemSDNode>(Node)->getAlignment()) && cast<MemSDNode>(Node)->getAlignment()) &&
"Unexpected unaligned loads/stores."); "Unexpected unaligned loads/stores.");

4
lib/Target/Mips/MipsISelDAGToDAG.h
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@@ -32,7 +32,7 @@ namespace llvm {
class MipsDAGToDAGISel : public SelectionDAGISel { class MipsDAGToDAGISel : public SelectionDAGISel {
public: public:
explicit MipsDAGToDAGISel(MipsTargetMachine &TM) explicit MipsDAGToDAGISel(MipsTargetMachine &TM)
: SelectionDAGISel(TM), Subtarget(TM.getSubtarget<MipsSubtarget>()) {} : SelectionDAGISel(TM), Subtarget(&TM.getSubtarget<MipsSubtarget>()) {}
// Pass Name // Pass Name
const char *getPassName() const override { const char *getPassName() const override {
@@ -46,7 +46,7 @@ protected:
/// Keep a pointer to the MipsSubtarget around so that we can make the right /// Keep a pointer to the MipsSubtarget around so that we can make the right
/// decision when generating code for different targets. /// decision when generating code for different targets.
const MipsSubtarget &Subtarget; const MipsSubtarget *Subtarget;
private: private:
// Include the pieces autogenerated from the target description. // Include the pieces autogenerated from the target description.

8
lib/Target/Mips/MipsInstrFPU.td
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@@ -57,13 +57,13 @@ let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
// Feature predicates. // Feature predicates.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def IsFP64bit : Predicate<"Subtarget.isFP64bit()">, def IsFP64bit : Predicate<"Subtarget->isFP64bit()">,
AssemblerPredicate<"FeatureFP64Bit">; AssemblerPredicate<"FeatureFP64Bit">;
def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">,
AssemblerPredicate<"!FeatureFP64Bit">; AssemblerPredicate<"!FeatureFP64Bit">;
def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">,
AssemblerPredicate<"FeatureSingleFloat">; AssemblerPredicate<"FeatureSingleFloat">;
def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,
AssemblerPredicate<"!FeatureSingleFloat">; AssemblerPredicate<"!FeatureSingleFloat">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

54
lib/Target/Mips/MipsInstrInfo.td
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@@ -146,61 +146,61 @@ def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Mips Instruction Predicate Definitions. // Mips Instruction Predicate Definitions.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def HasMips2 : Predicate<"Subtarget.hasMips2()">, def HasMips2 : Predicate<"Subtarget->hasMips2()">,
AssemblerPredicate<"FeatureMips2">; AssemblerPredicate<"FeatureMips2">;
def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">, def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
AssemblerPredicate<"FeatureMips3_32">; AssemblerPredicate<"FeatureMips3_32">;
def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">, def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
AssemblerPredicate<"FeatureMips3_32r2">; AssemblerPredicate<"FeatureMips3_32r2">;
def HasMips3 : Predicate<"Subtarget.hasMips3()">, def HasMips3 : Predicate<"Subtarget->hasMips3()">,
AssemblerPredicate<"FeatureMips3">; AssemblerPredicate<"FeatureMips3">;
def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">, def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
AssemblerPredicate<"FeatureMips4_32">; AssemblerPredicate<"FeatureMips4_32">;
def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">, def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
AssemblerPredicate<"FeatureMips4_32r2">; AssemblerPredicate<"FeatureMips4_32r2">;
def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">, def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
AssemblerPredicate<"FeatureMips5_32r2">; AssemblerPredicate<"FeatureMips5_32r2">;
def HasMips32 : Predicate<"Subtarget.hasMips32()">, def HasMips32 : Predicate<"Subtarget->hasMips32()">,
AssemblerPredicate<"FeatureMips32">; AssemblerPredicate<"FeatureMips32">;
def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
AssemblerPredicate<"FeatureMips32r2">; AssemblerPredicate<"FeatureMips32r2">;
def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">, def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
AssemblerPredicate<"FeatureMips32r6">; AssemblerPredicate<"FeatureMips32r6">;
def NotMips32r6 : Predicate<"!Subtarget.hasMips32r6()">, def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
AssemblerPredicate<"!FeatureMips32r6">; AssemblerPredicate<"!FeatureMips32r6">;
def IsGP64bit : Predicate<"Subtarget.isGP64bit()">, def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
AssemblerPredicate<"FeatureGP64Bit">; AssemblerPredicate<"FeatureGP64Bit">;
def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">, def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
AssemblerPredicate<"!FeatureGP64Bit">; AssemblerPredicate<"!FeatureGP64Bit">;
def HasMips64 : Predicate<"Subtarget.hasMips64()">, def HasMips64 : Predicate<"Subtarget->hasMips64()">,
AssemblerPredicate<"FeatureMips64">; AssemblerPredicate<"FeatureMips64">;
def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
AssemblerPredicate<"FeatureMips64r2">; AssemblerPredicate<"FeatureMips64r2">;
def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">, def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
AssemblerPredicate<"FeatureMips64r6">; AssemblerPredicate<"FeatureMips64r6">;
def NotMips64r6 : Predicate<"!Subtarget.hasMips64r6()">, def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
AssemblerPredicate<"!FeatureMips64r6">; AssemblerPredicate<"!FeatureMips64r6">;
def IsN64 : Predicate<"Subtarget.isABI_N64()">, def IsN64 : Predicate<"Subtarget->isABI_N64()">,
AssemblerPredicate<"FeatureN64">; AssemblerPredicate<"FeatureN64">;
def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
AssemblerPredicate<"FeatureMips16">; AssemblerPredicate<"FeatureMips16">;
def HasCnMips : Predicate<"Subtarget.hasCnMips()">, def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
AssemblerPredicate<"FeatureCnMips">; AssemblerPredicate<"FeatureCnMips">;
def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
AssemblerPredicate<"FeatureMips32">; AssemblerPredicate<"FeatureMips32">;
def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
AssemblerPredicate<"FeatureMips32">; AssemblerPredicate<"FeatureMips32">;
def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
AssemblerPredicate<"!FeatureMips16">; AssemblerPredicate<"!FeatureMips16">;
def NotDSP : Predicate<"!Subtarget.hasDSP()">; def NotDSP : Predicate<"!Subtarget->hasDSP()">;
def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">, def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
AssemblerPredicate<"FeatureMicroMips">; AssemblerPredicate<"FeatureMicroMips">;
def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">, def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
AssemblerPredicate<"!FeatureMicroMips">; AssemblerPredicate<"!FeatureMicroMips">;
def IsLE : Predicate<"Subtarget.isLittle()">; def IsLE : Predicate<"Subtarget->isLittle()">;
def IsBE : Predicate<"!Subtarget.isLittle()">; def IsBE : Predicate<"!Subtarget->isLittle()">;
def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">; def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Mips GPR size adjectives. // Mips GPR size adjectives.

2
lib/Target/Mips/MipsMSAInstrFormats.td
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@@ -7,7 +7,7 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def HasMSA : Predicate<"Subtarget.hasMSA()">, def HasMSA : Predicate<"Subtarget->hasMSA()">,
AssemblerPredicate<"FeatureMSA">; AssemblerPredicate<"FeatureMSA">;
class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {

24
lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View File

@@ -37,7 +37,7 @@ using namespace llvm;
#define DEBUG_TYPE "mips-isel" #define DEBUG_TYPE "mips-isel"
bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
if (Subtarget.inMips16Mode()) if (Subtarget->inMips16Mode())
return false; return false;
return MipsDAGToDAGISel::runOnMachineFunction(MF); return MipsDAGToDAGISel::runOnMachineFunction(MF);
} }
@@ -134,7 +134,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg(); unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
const TargetRegisterClass *RC; const TargetRegisterClass *RC;
if (Subtarget.isABI_N64()) if (Subtarget->isABI_N64())
RC = (const TargetRegisterClass*)&Mips::GPR64RegClass; RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
else else
RC = (const TargetRegisterClass*)&Mips::GPR32RegClass; RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
@@ -142,7 +142,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
V0 = RegInfo.createVirtualRegister(RC); V0 = RegInfo.createVirtualRegister(RC);
V1 = RegInfo.createVirtualRegister(RC); V1 = RegInfo.createVirtualRegister(RC);
if (Subtarget.isABI_N64()) { if (Subtarget->isABI_N64()) {
MF.getRegInfo().addLiveIn(Mips::T9_64); MF.getRegInfo().addLiveIn(Mips::T9_64);
MBB.addLiveIn(Mips::T9_64); MBB.addLiveIn(Mips::T9_64);
@@ -174,7 +174,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
MF.getRegInfo().addLiveIn(Mips::T9); MF.getRegInfo().addLiveIn(Mips::T9);
MBB.addLiveIn(Mips::T9); MBB.addLiveIn(Mips::T9);
if (Subtarget.isABI_N32()) { if (Subtarget->isABI_N32()) {
// lui $v0, %hi(%neg(%gp_rel(fname))) // lui $v0, %hi(%neg(%gp_rel(fname)))
// addu $v1, $v0, $t9 // addu $v1, $v0, $t9
// addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
@@ -187,7 +187,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
return; return;
} }
assert(Subtarget.isABI_O32()); assert(Subtarget->isABI_O32());
// For O32 ABI, the following instruction sequence is emitted to initialize // For O32 ABI, the following instruction sequence is emitted to initialize
// the global base register: // the global base register:
@@ -408,7 +408,7 @@ bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
// * MSA is enabled // * MSA is enabled
// * N is a ISD::BUILD_VECTOR representing a constant splat // * N is a ISD::BUILD_VECTOR representing a constant splat
bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const { bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
if (!Subtarget.hasMSA()) if (!Subtarget->hasMSA())
return false; return false;
BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N); BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
@@ -422,7 +422,7 @@ bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
HasAnyUndefs, 8, HasAnyUndefs, 8,
!Subtarget.isLittle())) !Subtarget->isLittle()))
return false; return false;
Imm = SplatValue; Imm = SplatValue;
@@ -648,7 +648,7 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
} }
case ISD::ADDE: { case ISD::ADDE: {
if (Subtarget.hasDSP()) // Select DSP instructions, ADDSC and ADDWC. if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
break; break;
SDValue InFlag = Node->getOperand(2); SDValue InFlag = Node->getOperand(2);
Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node); Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
@@ -658,11 +658,11 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
case ISD::ConstantFP: { case ISD::ConstantFP: {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node); ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
if (Subtarget.isGP64bit()) { if (Subtarget->isGP64bit()) {
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
Mips::ZERO_64, MVT::i64); Mips::ZERO_64, MVT::i64);
Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero); Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
} else if (Subtarget.isFP64bit()) { } else if (Subtarget->isFP64bit()) {
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
Mips::ZERO, MVT::i32); Mips::ZERO, MVT::i32);
Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64, Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
@@ -813,12 +813,12 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
EVT ResVecTy = BVN->getValueType(0); EVT ResVecTy = BVN->getValueType(0);
EVT ViaVecTy; EVT ViaVecTy;
if (!Subtarget.hasMSA() || !BVN->getValueType(0).is128BitVector()) if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
return std::make_pair(false, nullptr); return std::make_pair(false, nullptr);
if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
HasAnyUndefs, 8, HasAnyUndefs, 8,
!Subtarget.isLittle())) !Subtarget->isLittle()))
return std::make_pair(false, nullptr); return std::make_pair(false, nullptr);
switch (SplatBitSize) { switch (SplatBitSize) {