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[SparcV9] Adds support for branch on integer register instructions (BPr) and conditional moves on integer register (MOVr/FMOVr).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202628 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
2014-03-02 09:46:56 +00:00
parent a9fe27ffb3
commit 2871375882
9 changed files with 243 additions and 1 deletions
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20
lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
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@@ -64,6 +64,10 @@ public:
unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
};
} // end anonymous namespace
@@ -192,6 +196,22 @@ getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
(MCFixupKind)Sparc::fixup_sparc_br19));
return 0;
}
unsigned SparcMCCodeEmitter::
getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)Sparc::fixup_sparc_br16_2));
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)Sparc::fixup_sparc_br16_14));
return 0;
}
#include "SparcGenMCCodeEmitter.inc"