mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-09 07:24:39 +00:00
now that fsel is formed during legalization, this code is dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23084 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@ -694,18 +694,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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}
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}
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break;
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break;
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}
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}
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case ISD::ConstantFP: { // FIXME: this should get sucked into the legalizer
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Constant *CFP = ConstantFP::get(Type::FloatTy,
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cast<ConstantFPSDNode>(N)->getValue());
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SDOperand CPN = CurDAG->getConstantPool(CFP, MVT::i32);
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SDOperand Tmp;
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if (PICEnabled)
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Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPN);
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else
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Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPN);
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CurDAG->SelectNodeTo(N, PPC::LFS, N->getValueType(0), CPN, Tmp);
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break;
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}
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case ISD::UNDEF:
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case ISD::UNDEF:
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if (N->getValueType(0) == MVT::i32)
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if (N->getValueType(0) == MVT::i32)
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CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);
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CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);
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@ -97,7 +97,6 @@ public:
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SDOperand BuildUDIVSequence(SDOperand N);
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SDOperand BuildUDIVSequence(SDOperand N);
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unsigned getGlobalBaseReg();
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unsigned getGlobalBaseReg();
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unsigned getConstDouble(double floatVal, unsigned Result);
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void MoveCRtoGPR(unsigned CCReg, ISD::CondCode CC, unsigned Result);
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void MoveCRtoGPR(unsigned CCReg, ISD::CondCode CC, unsigned Result);
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bool SelectBitfieldInsert(SDOperand OR, unsigned Result);
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bool SelectBitfieldInsert(SDOperand OR, unsigned Result);
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unsigned FoldIfWideZeroExtend(SDOperand N);
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unsigned FoldIfWideZeroExtend(SDOperand N);
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@ -443,23 +442,6 @@ unsigned ISel::getGlobalBaseReg() {
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return GlobalBaseReg;
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return GlobalBaseReg;
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}
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}
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/// getConstDouble - Loads a floating point value into a register, via the
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/// Constant Pool. Optionally takes a register in which to load the value.
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unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
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unsigned Tmp1 = MakeIntReg();
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if (0 == Result) Result = MakeFPReg();
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MachineConstantPool *CP = BB->getParent()->getConstantPool();
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ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, doubleVal);
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unsigned CPI = CP->getConstantPoolIndex(CFP);
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if (PICEnabled)
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BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
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.addConstantPoolIndex(CPI);
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else
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BuildMI(BB, PPC::LIS, 1, Tmp1).addConstantPoolIndex(CPI);
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BuildMI(BB, PPC::LFD, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
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return Result;
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}
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/// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result. If
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/// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result. If
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/// Inv is true, then invert the result.
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/// Inv is true, then invert the result.
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void ISel::MoveCRtoGPR(unsigned CCReg, ISD::CondCode CC, unsigned Result){
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void ISel::MoveCRtoGPR(unsigned CCReg, ISD::CondCode CC, unsigned Result){
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@ -1602,72 +1584,6 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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case ISD::SELECT_CC: {
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case ISD::SELECT_CC: {
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ISD::CondCode CC = cast<CondCodeSDNode>(N.getOperand(4))->get();
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ISD::CondCode CC = cast<CondCodeSDNode>(N.getOperand(4))->get();
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if (!MVT::isInteger(N.getOperand(0).getValueType()) &&
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!MVT::isInteger(N.getOperand(2).getValueType()) &&
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CC != ISD::SETEQ && CC != ISD::SETNE) {
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MVT::ValueType VT = N.getOperand(0).getValueType();
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unsigned TV = SelectExpr(N.getOperand(2)); // Use if TRUE
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unsigned FV = SelectExpr(N.getOperand(3)); // Use if FALSE
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N.getOperand(1));
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if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
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switch(CC) {
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default: assert(0 && "Invalid FSEL condition"); abort();
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case ISD::SETULT:
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case ISD::SETLT:
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std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
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case ISD::SETUGE:
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case ISD::SETGE:
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Tmp1 = SelectExpr(N.getOperand(0)); // Val to compare against
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(TV).addReg(FV);
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return Result;
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case ISD::SETUGT:
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case ISD::SETGT:
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std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
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case ISD::SETULE:
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case ISD::SETLE: {
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if (N.getOperand(0).getOpcode() == ISD::FNEG) {
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
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} else {
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Tmp2 = MakeReg(VT);
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Tmp1 = SelectExpr(N.getOperand(0)); // Val to compare against
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BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
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}
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(TV).addReg(FV);
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return Result;
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}
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}
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} else {
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Opc = (MVT::f64 == VT) ? PPC::FSUB : PPC::FSUBS;
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Tmp1 = SelectExpr(N.getOperand(0)); // Val to compare against
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Tmp2 = SelectExpr(N.getOperand(1));
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Tmp3 = MakeReg(VT);
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switch(CC) {
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default: assert(0 && "Invalid FSEL condition"); abort();
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case ISD::SETULT:
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case ISD::SETLT:
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BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
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return Result;
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case ISD::SETUGE:
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case ISD::SETGE:
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BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
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return Result;
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case ISD::SETUGT:
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case ISD::SETGT:
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BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
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return Result;
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case ISD::SETULE:
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case ISD::SETLE:
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BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
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return Result;
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}
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}
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assert(0 && "Should never get here");
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}
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// handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
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// handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
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@ -1765,12 +1681,6 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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return Result;
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return Result;
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}
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}
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case ISD::ConstantFP: {
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ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
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Result = getConstDouble(CN->getValue(), Result);
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return Result;
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}
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case ISD::FNEG:
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case ISD::FNEG:
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if (!NoExcessFPPrecision &&
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if (!NoExcessFPPrecision &&
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ISD::ADD == N.getOperand(0).getOpcode() &&
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ISD::ADD == N.getOperand(0).getOpcode() &&
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