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Cleanup and factoring of mips16 tablegen classes. Make register classes

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CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157730 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2012-05-31 02:59:44 +00:00
parent feba19309d
commit 28ee4fdf20
3 changed files with 89 additions and 61 deletions
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5
lib/Target/Mips/MipsISelLowering.cpp
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@@ -103,6 +103,11 @@ MipsTargetLowering(MipsTargetMachine &TM)
if (HasMips64)
addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
if (Subtarget->inMips16Mode()) {
addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
addRegisterClass(MVT::i32, &Mips::CPURARegRegClass);
}
if (!TM.Options.UseSoftFloat) {
addRegisterClass(MVT::f32, &Mips::FGR32RegClass);