mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Remove the SystemZ backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142878 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
@@ -1,439 +0,0 @@
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//===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SystemZ implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "SystemZInstrBuilder.h"
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#include "SystemZInstrInfo.h"
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#include "SystemZMachineFunctionInfo.h"
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#include "SystemZTargetMachine.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#define GET_INSTRINFO_CTOR
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#include "SystemZGenInstrInfo.inc"
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using namespace llvm;
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SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
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: SystemZGenInstrInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
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RI(tm, *this), TM(tm) {
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}
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/// isGVStub - Return true if the GV requires an extra load to get the
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/// real address.
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static inline bool isGVStub(GlobalValue *GV, SystemZTargetMachine &TM) {
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return TM.getSubtarget<SystemZSubtarget>().GVRequiresExtraLoad(GV, TM, false);
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}
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void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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unsigned Opc = 0;
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if (RC == &SystemZ::GR32RegClass ||
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RC == &SystemZ::ADDR32RegClass)
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Opc = SystemZ::MOV32mr;
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else if (RC == &SystemZ::GR64RegClass ||
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RC == &SystemZ::ADDR64RegClass) {
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Opc = SystemZ::MOV64mr;
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} else if (RC == &SystemZ::FP32RegClass) {
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Opc = SystemZ::FMOV32mr;
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} else if (RC == &SystemZ::FP64RegClass) {
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Opc = SystemZ::FMOV64mr;
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} else if (RC == &SystemZ::GR64PRegClass) {
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Opc = SystemZ::MOV64Pmr;
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} else if (RC == &SystemZ::GR128RegClass) {
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Opc = SystemZ::MOV128mr;
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} else
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llvm_unreachable("Unsupported regclass to store");
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addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
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.addReg(SrcReg, getKillRegState(isKill));
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}
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void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const{
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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unsigned Opc = 0;
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if (RC == &SystemZ::GR32RegClass ||
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RC == &SystemZ::ADDR32RegClass)
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Opc = SystemZ::MOV32rm;
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else if (RC == &SystemZ::GR64RegClass ||
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RC == &SystemZ::ADDR64RegClass) {
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Opc = SystemZ::MOV64rm;
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} else if (RC == &SystemZ::FP32RegClass) {
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Opc = SystemZ::FMOV32rm;
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} else if (RC == &SystemZ::FP64RegClass) {
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Opc = SystemZ::FMOV64rm;
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} else if (RC == &SystemZ::GR64PRegClass) {
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Opc = SystemZ::MOV64Prm;
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} else if (RC == &SystemZ::GR128RegClass) {
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Opc = SystemZ::MOV128rm;
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} else
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llvm_unreachable("Unsupported regclass to load");
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addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
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}
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void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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unsigned Opc;
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if (SystemZ::GR64RegClass.contains(DestReg, SrcReg))
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Opc = SystemZ::MOV64rr;
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else if (SystemZ::GR32RegClass.contains(DestReg, SrcReg))
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Opc = SystemZ::MOV32rr;
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else if (SystemZ::GR64PRegClass.contains(DestReg, SrcReg))
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Opc = SystemZ::MOV64rrP;
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else if (SystemZ::GR128RegClass.contains(DestReg, SrcReg))
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Opc = SystemZ::MOV128rr;
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else if (SystemZ::FP32RegClass.contains(DestReg, SrcReg))
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Opc = SystemZ::FMOV32rr;
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else if (SystemZ::FP64RegClass.contains(DestReg, SrcReg))
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Opc = SystemZ::FMOV64rr;
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else
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llvm_unreachable("Impossible reg-to-reg copy");
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BuildMI(MBB, I, DL, get(Opc), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case SystemZ::MOV32rm:
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case SystemZ::MOV32rmy:
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case SystemZ::MOV64rm:
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case SystemZ::MOVSX32rm8:
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case SystemZ::MOVSX32rm16y:
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case SystemZ::MOVSX64rm8:
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case SystemZ::MOVSX64rm16:
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case SystemZ::MOVSX64rm32:
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case SystemZ::MOVZX32rm8:
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case SystemZ::MOVZX32rm16:
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case SystemZ::MOVZX64rm8:
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case SystemZ::MOVZX64rm16:
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case SystemZ::MOVZX64rm32:
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case SystemZ::FMOV32rm:
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case SystemZ::FMOV32rmy:
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case SystemZ::FMOV64rm:
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case SystemZ::FMOV64rmy:
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case SystemZ::MOV64Prm:
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case SystemZ::MOV64Prmy:
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case SystemZ::MOV128rm:
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if (MI->getOperand(1).isFI() &&
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MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
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MI->getOperand(2).getImm() == 0 && MI->getOperand(3).getReg() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case SystemZ::MOV32mr:
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case SystemZ::MOV32mry:
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case SystemZ::MOV64mr:
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case SystemZ::MOV32m8r:
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case SystemZ::MOV32m8ry:
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case SystemZ::MOV32m16r:
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case SystemZ::MOV32m16ry:
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case SystemZ::MOV64m8r:
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case SystemZ::MOV64m8ry:
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case SystemZ::MOV64m16r:
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case SystemZ::MOV64m16ry:
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case SystemZ::MOV64m32r:
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case SystemZ::MOV64m32ry:
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case SystemZ::FMOV32mr:
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case SystemZ::FMOV32mry:
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case SystemZ::FMOV64mr:
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case SystemZ::FMOV64mry:
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case SystemZ::MOV64Pmr:
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case SystemZ::MOV64Pmry:
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case SystemZ::MOV128mr:
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if (MI->getOperand(0).isFI() &&
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MI->getOperand(1).isImm() && MI->getOperand(2).isReg() &&
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MI->getOperand(1).getImm() == 0 && MI->getOperand(2).getReg() == 0) {
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FrameIndex = MI->getOperand(0).getIndex();
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return MI->getOperand(3).getReg();
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}
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break;
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}
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return 0;
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}
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bool SystemZInstrInfo::
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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assert(Cond.size() == 1 && "Invalid Xbranch condition!");
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SystemZCC::CondCodes CC = static_cast<SystemZCC::CondCodes>(Cond[0].getImm());
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Cond[0].setImm(getOppositeCondition(CC));
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return false;
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}
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bool SystemZInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
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const MCInstrDesc &MCID = MI->getDesc();
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if (!MCID.isTerminator()) return false;
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// Conditional branch is a special case.
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if (MCID.isBranch() && !MCID.isBarrier())
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return true;
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if (!MCID.isPredicable())
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return true;
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return !isPredicated(MI);
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}
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bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// Start from the bottom of the block and work up, examining the
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// terminator instructions.
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MachineBasicBlock::iterator I = MBB.end();
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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// Working from the bottom, when we see a non-terminator
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// instruction, we're done.
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if (!isUnpredicatedTerminator(I))
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break;
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// A terminator that isn't a branch can't easily be handled
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// by this analysis.
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if (!I->getDesc().isBranch())
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return true;
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// Handle unconditional branches.
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if (I->getOpcode() == SystemZ::JMP) {
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if (!AllowModify) {
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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// If the block has any instructions after a JMP, delete them.
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while (llvm::next(I) != MBB.end())
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llvm::next(I)->eraseFromParent();
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Cond.clear();
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FBB = 0;
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// Delete the JMP if it's equivalent to a fall-through.
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if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
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TBB = 0;
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I->eraseFromParent();
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I = MBB.end();
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continue;
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}
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// TBB is used to indicate the unconditinal destination.
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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// Handle conditional branches.
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SystemZCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
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if (BranchCode == SystemZCC::INVALID)
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return true; // Can't handle indirect branch.
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// Working from the bottom, handle the first conditional branch.
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if (Cond.empty()) {
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FBB = TBB;
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TBB = I->getOperand(0).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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continue;
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}
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// Handle subsequent conditional branches. Only handle the case where all
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// conditional branches branch to the same destination.
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assert(Cond.size() == 1);
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assert(TBB);
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// Only handle the case where all conditional branches branch to
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// the same destination.
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if (TBB != I->getOperand(0).getMBB())
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return true;
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SystemZCC::CondCodes OldBranchCode = (SystemZCC::CondCodes)Cond[0].getImm();
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// If the conditions are the same, we can leave them alone.
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if (OldBranchCode == BranchCode)
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continue;
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return true;
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}
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return false;
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}
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unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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unsigned Count = 0;
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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if (I->getOpcode() != SystemZ::JMP &&
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getCondFromBranchOpc(I->getOpcode()) == SystemZCC::INVALID)
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break;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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++Count;
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}
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return Count;
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}
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unsigned
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SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 1 || Cond.size() == 0) &&
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"SystemZ branch conditions have one component!");
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if (Cond.empty()) {
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// Unconditional branch?
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assert(!FBB && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(TBB);
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return 1;
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}
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// Conditional branch.
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unsigned Count = 0;
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SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm();
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BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
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++Count;
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if (FBB) {
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// Two-way Conditional branch. Insert the second branch.
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BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(FBB);
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++Count;
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}
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return Count;
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}
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const MCInstrDesc&
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SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
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switch (CC) {
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default:
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llvm_unreachable("Unknown condition code!");
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case SystemZCC::O: return get(SystemZ::JO);
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case SystemZCC::H: return get(SystemZ::JH);
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case SystemZCC::NLE: return get(SystemZ::JNLE);
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case SystemZCC::L: return get(SystemZ::JL);
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case SystemZCC::NHE: return get(SystemZ::JNHE);
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case SystemZCC::LH: return get(SystemZ::JLH);
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case SystemZCC::NE: return get(SystemZ::JNE);
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case SystemZCC::E: return get(SystemZ::JE);
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case SystemZCC::NLH: return get(SystemZ::JNLH);
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case SystemZCC::HE: return get(SystemZ::JHE);
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case SystemZCC::NL: return get(SystemZ::JNL);
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case SystemZCC::LE: return get(SystemZ::JLE);
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case SystemZCC::NH: return get(SystemZ::JNH);
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case SystemZCC::NO: return get(SystemZ::JNO);
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}
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}
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SystemZCC::CondCodes
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SystemZInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
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switch (Opc) {
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default: return SystemZCC::INVALID;
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case SystemZ::JO: return SystemZCC::O;
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case SystemZ::JH: return SystemZCC::H;
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case SystemZ::JNLE: return SystemZCC::NLE;
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case SystemZ::JL: return SystemZCC::L;
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case SystemZ::JNHE: return SystemZCC::NHE;
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case SystemZ::JLH: return SystemZCC::LH;
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case SystemZ::JNE: return SystemZCC::NE;
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case SystemZ::JE: return SystemZCC::E;
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case SystemZ::JNLH: return SystemZCC::NLH;
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case SystemZ::JHE: return SystemZCC::HE;
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case SystemZ::JNL: return SystemZCC::NL;
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case SystemZ::JLE: return SystemZCC::LE;
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case SystemZ::JNH: return SystemZCC::NH;
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case SystemZ::JNO: return SystemZCC::NO;
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}
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}
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SystemZCC::CondCodes
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SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const {
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switch (CC) {
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default:
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llvm_unreachable("Invalid condition!");
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case SystemZCC::O: return SystemZCC::NO;
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case SystemZCC::H: return SystemZCC::NH;
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case SystemZCC::NLE: return SystemZCC::LE;
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case SystemZCC::L: return SystemZCC::NL;
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case SystemZCC::NHE: return SystemZCC::HE;
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case SystemZCC::LH: return SystemZCC::NLH;
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case SystemZCC::NE: return SystemZCC::E;
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case SystemZCC::E: return SystemZCC::NE;
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case SystemZCC::NLH: return SystemZCC::LH;
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case SystemZCC::HE: return SystemZCC::NHE;
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case SystemZCC::NL: return SystemZCC::L;
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case SystemZCC::LE: return SystemZCC::NLE;
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case SystemZCC::NH: return SystemZCC::H;
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case SystemZCC::NO: return SystemZCC::O;
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}
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}
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const MCInstrDesc&
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SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
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switch (Opc) {
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default:
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llvm_unreachable("Don't have long disp version of this instruction");
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case SystemZ::MOV32mr: return get(SystemZ::MOV32mry);
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case SystemZ::MOV32rm: return get(SystemZ::MOV32rmy);
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case SystemZ::MOVSX32rm16: return get(SystemZ::MOVSX32rm16y);
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case SystemZ::MOV32m8r: return get(SystemZ::MOV32m8ry);
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case SystemZ::MOV32m16r: return get(SystemZ::MOV32m16ry);
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case SystemZ::MOV64m8r: return get(SystemZ::MOV64m8ry);
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case SystemZ::MOV64m16r: return get(SystemZ::MOV64m16ry);
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case SystemZ::MOV64m32r: return get(SystemZ::MOV64m32ry);
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case SystemZ::MOV8mi: return get(SystemZ::MOV8miy);
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case SystemZ::MUL32rm: return get(SystemZ::MUL32rmy);
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case SystemZ::CMP32rm: return get(SystemZ::CMP32rmy);
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case SystemZ::UCMP32rm: return get(SystemZ::UCMP32rmy);
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case SystemZ::FMOV32mr: return get(SystemZ::FMOV32mry);
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case SystemZ::FMOV64mr: return get(SystemZ::FMOV64mry);
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case SystemZ::FMOV32rm: return get(SystemZ::FMOV32rmy);
|
||||
case SystemZ::FMOV64rm: return get(SystemZ::FMOV64rmy);
|
||||
case SystemZ::MOV64Pmr: return get(SystemZ::MOV64Pmry);
|
||||
case SystemZ::MOV64Prm: return get(SystemZ::MOV64Prmy);
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user